TDC1011_15 Datasheet, PDF (7/49 Pages) Texas Instruments – TDC1011 Single Channel Ultrasonic Sensing Analog Front End (AFE) for Level Sensing,Concentration Sensing Applications

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TDC1011
SNAS662 – JULY 2015
6.6 Timing Requirements
T_A = 25°C, V_DD = V_IO = 3.7 V and ƒ_SCLK = 1 MHz (unless otherwise noted).
MIN
NOM
MAX
ƒ_SCLK
t₁
t₂
t₃
t₄
t₅
t₆
t₇
t₈
t₉
t_r / t_f
Serial clock frequency
High period, SCLK
Low period, SCLK
Set-up time, nCS to SCLK
Set-up time, SDI to SCLK
Hold time, SCLK to SDI
SCLK transition to SDO valid time
Hold time, SCLK transition to nCS rising edge
nCS inactive
Hold time, SCLK transition to nCS falling edge
Signal rise and fall times⁽¹⁾
26
16
16
10
12
12
16
10
17
10
1.8
(1) The slew rate is measured from 10% to 90% and is represented by the average of the rising and falling slew rates.
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK
CSB
t₉
t₃
t₂
t₁
t₇
t₄ t₅
t₈
D₁₅
D₁₄
D₀
t₆
90%
Prior D_{15 10%}
t_r
90%
Prior D_{1 10%}
Prior D₀
t_f
Figure 1. SPI Timing Diagram
6.7 Switching Characteristics
T_A = 25°C, V_DD = V_IO = 3.7 V, ƒ_CLKIN = 8 MHz.
PARAMETER
TEST CONDITIONS
START, STOP, ENABLE, RESET, CLOCKIN, TRIGGER, ERR
TX_FREQ_DIV = 2h, NUM_TX = 1
PW_START Pulse width for START signal TX_FREQ_DIV = 2h, NUM_TX = 2
TX_FREQ_DIV = 2h, NUM_TX ≥ 3
t_r / t_f
START
Rise/fall time for START
signal
20% to 80%, 20-pF load
t_r / t_{f STOP} Rise/fall time for STOP signal 20% to 80%, 20-pF load
ƒ_CLKIN
Maximum CLKIN input
frequency
t_r / t_{f CLKIN} CLKIN input rise/fall time⁽¹⁾ 20% to 80%
t_r / t_{f TRIG}
TRIGGER input rise/fall
time ⁽¹⁾
20% to 80%
t_{EN_TRIG} Enable to trigger wait time⁽¹⁾
t_{RES_TRIG} Reset to trigger wait time⁽¹⁾
TX_FREQ_DIV = 2h (see TX/RX Measurement
Sequencing and Timing)
(1) Specified by design.
MIN
TYP
MAX UNIT
1
μs
2
μs
3
μs
0.25
ns
0.25
ns
16
MHz
10
ns
10
ns
50
ns
3.05
μs
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