TDC1011_15 Datasheet, PDF (27/49 Pages) Texas Instruments – TDC1011 Single Channel Ultrasonic Sensing Analog Front End (AFE) for Level Sensing,Concentration Sensing Applications

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Device Function Description (continued)
TDC1011
SNAS662 – JULY 2015
NOTE
If the FORCE_SHORT_TOF bit = 1, the measurement sequencing will behave as a Short
TOF Measurement, thus overriding the setting of the TIMING_REG field.
8.4.6.3 Standard TOF Measurement with Power Blanking
TRIG
Analog OFF
Analog ON
Echo listen period
TX
(see Note A)
START
(see Note B)
RX
(see Note C)
STOP
READY
TRANSMIT
NUM_TX x T1
WAIT
(TIMING_REG ± 30) x 8 x T0
COMMON-MODE
128 x T0
AUTOZERO
2^{AUTOZERO_PERIOD} x 64 x T0
ECHO LISTEN
END READY
2^{TOF_TIMEOUT_CTRL} x 128 x T0 1 x T1
A. Clock alignment.
B. If NUM_TX < 3, the width of the START pulse is equal to NUM_TX × T1. If NUM_TX ≥ 3, the width of the START
pulse is equal to 3 × T1.
C. Common-mode settling time.
Figure 39. Standard TOF Measurement with Blanking Enabled
The power blanking sequence is a variation to the standard TOF measurement sequence, and can be enabled
by setting the BLANKING bit to 1. In addition, all other conditions described in the Standard TOF Measurement
should be met. The BLANKING bit can be found in the CONFIG_3 register.
Power blanking allows the device to remain in a low-power state while the TX signals propagate to the RX
transducer in situations when the expected time-of-flight is long. Power blanking uses the TIMING_REG to
control a wait time between the transmit sequence and the receive sequence, during which, the complete RX
chain is disabled, as shown in Figure 39. The TIMING_REG is a 10-bit wide field, with its 2 most significant bits
located in the TOF_1 register, and the 7 least significant bits located in the TOF_0 register.
8.4.6.4 Common-mode Reference Settling Time
The duration of the common-mode settling time is defined by the VCOM capacitor. With a 10-nF VCOM
capacitor, the common-mode reference requires 16 µs to settle. On the other hand, the duration of the common-
mode settling window is defined as 128 × T0, where the time unit T0 is determined by the external clock
frequency and the value of the CLOCKIN_DIV bit, as explained in the Timing Control and Frequency Scaling
(CLKIN) section.
A frequency of 8 MHz will result in a settling window of 128 × 1 / 8 MHz, which equals to 16 µs. Increasing the
value of the VCOM capacitor will increase the common-mode settling time, but for the same 8-MHz frequency,
the duration of the common-mode settling window will remain at 16 µs. In such situation, the common-mode
reference will take multiple TOF cycles to reach its final value when starting from zero initial conditions.
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