TDC1011_15 Datasheet, PDF (29/49 Pages) Texas Instruments – TDC1011 Single Channel Ultrasonic Sensing Analog Front End (AFE) for Level Sensing,Concentration Sensing Applications

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TDC1011
SNAS662 – JULY 2015
Programming (continued)
The communication on the SPI bus normally supports write and read transactions. A write transaction consists of
a single write command byte, followed by single data byte. A read transaction consists of a single read command
byte followed by 8 SCLK cycles. The write and read command bytes consist of 1 reserved bit, a 1-bit instruction,
and a 6-bit register address. Figure 40 shows the SPI protocol for a transaction involving one byte of data (read
or write).
CSB
SCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
COMMAND FIELD
DATA FIELD
SDI
MSB
LSB
c7
c6
c5
c4
c3
c2
c1
c0
d7
d6
d5
d4
d3
d2
d1
d0
SDO
resvd R/W
Address (6 bits)
Write Data (8-bits)
MSB
d7
d6
d5
d4
d3
d2
LSB
d1
d0
R/W = Instruction
0: Read
1: Write
Note: Specifying any value other than zero in bit[7] of the command byte is prohibited.
Figure 40. SPI Protocol
Read Data (8-bits)
8.5.1.1 Chip Select Bar (CSB)
CSB is an active-low signal and needs to be low throughout a transaction. That is, CSB should not pulse
between the command byte and the data byte of a single transaction.
De-asserting CSB always terminates an ongoing transaction, even if it is not yet complete. Re-asserting CSB will
always bring the device into a state ready for the next transaction, regardless of the termination status of a
previous transaction.
8.5.1.2 Serial Clock (SCLK)
SCLK can idle high or low. It is recommended to keep SCLK as clean as possible to prevent glitches from
corrupting the SPI frame.
8.5.1.3 Serial Data Input (SDI)
SDI is driven by the SPI master by sending the command and the data byte to configure the AFE.
8.5.1.4 Serial Data Output (SDO)
SDO is driven by the AFE when the SPI master initiates a read transaction.
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