TDC1011_15 Datasheet, PDF (24/49 Pages) Texas Instruments – TDC1011 Single Channel Ultrasonic Sensing Analog Front End (AFE) for Level Sensing,Concentration Sensing Applications

TDC1011
SNAS662 – JULY 2015
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Device Function Description (continued)
The rising edge of a STOP pulse is generated by a zero-crossing event. As in the Single Echo Receive Mode,
the threshold comparator qualifies the next zero-cross after an RX amplitude smaller than the programmed
threshold voltage is detected. The STOP pulse will extend until a zero-cross after the RX amplitude is no longer
smaller than the threshold voltage (see Figure 35).
Zero-crossing detected
after threshold exceeded
Signal zero-crossing without
exceeding threshold
COMPIN
VCOM
Programmed
threshold
Output on
STOP pin
Signal exceeds
threshold
Figure 35. Multiple Echo Receive Mode (Zoom-in)
If the number of expected pulses programmed in NUM_RX is not received or the time-of-flight operation times
out, the TDC1011 will indicate an error condition in the ERROR_FLAGS register and will set the ERRB pin low.
8.4.5 Timing
8.4.5.1 Timing Control and Frequency Scaling (CLKIN)
0x09[2] ± CLOCKIN_DIV
CLKIN ¦_CLKIN
O 2^CLOCKIN_DIV
1
¦₀
T0 = Š
¦₀
O 2^{TX_FREQ_DIV+1}
¦₁
1
T1 = Š
¦₁
0x00[7:5] ± TX_FREQ_DIV
Figure 36. External Clock Division Tree
All transmit and receive function sequencing is synchronous to the external clock applied to the CLKIN pin. The
external clock is divided to generate two internal clocks with corresponding time periods denoted as T0 and T1 in
Figure 36. The division factor used to generate T0 is controlled with the CLOCKIN_DIV bit in the CLOCK_RATE
register. The division factor used to generate T1 is controlled with the TX_FREQ_DIV field located in the
CONFIG_0 register.
The SPI block is synchronous with the clock applied to the SCLK pin, and it is independent of the clock applied
to CLKIN. See the Serial Peripheral Interface (SPI) section for a complete description of the SPI block.
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