TDC1011_15 Datasheet, PDF (42/49 Pages) Texas Instruments – TDC1011 Single Channel Ultrasonic Sensing Analog Front End (AFE) for Level Sensing,Concentration Sensing Applications

TDC1011
SNAS662 – JULY 2015
11 Layout
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11.1 Layout Guidelines
• In a 4-layer board design, the recommended layer stack order from top to bottom is: signal, ground, power
and signal.
• Bypass capacitors should be placed in close proximity to the VDD and VIO pins.
• The length of the START and STOP traces from the DUT to the stopwatch/MCU should be matched to
prevent uneven signal delays. Also, avoid unnecessary via-holes on these traces and keep the routing as
short/direct as possible to minimize parasitic capacitance on the PCB.
• Match the length (or resistance) of the traces leading to the RTD sensors. PCB series resistance will be
added in series to the RTD sensors.
• Route the SPI signal traces close together. Place a series resistor at the source of SDO (close to the DUT)
and series resistors at the sources of SDI, SCLK and CSB (close to the master MCU).
11.2 Layout Example
VIA to Ground Plane
VIA to Bottom or Internal Layer
Top Layer
Bottom Layer
GND
NC
1
RTD1
GND
To RTDs: Match trace
length (resistance)
GND
RX
VCOM
LNAOUT
PGAIN
PGAOUT
COMPIN
RTD1
RTD2
GND
RREF
RES
RTD2
GND
ERRB
START
STOP
TX
NC
GND
CLKIN
VDD
VDD
VIO
SDO
SDI
CSB
SCLK
RESET
TRIGGER
EN
System Clock
MCU
SPI Master
MCU
I/Os
Trigger:stop
watch/MCU
MCU
I/Os
Figure 57. TDC1011 Board Layout (Capacitive Feedback Mode)
Matched
trace
length to
stopwatch
/MCU
42
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