TDC1011_15 Datasheet, PDF (30/49 Pages) Texas Instruments – TDC1011 Single Channel Ultrasonic Sensing Analog Front End (AFE) for Level Sensing,Concentration Sensing Applications

TDC1011
SNAS662 – JULY 2015
8.6 Register Maps
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NOTE
• Reserved bits must be written to 0 unless otherwise indicated.
• Read-back value of reserved bits and registers is unspecified and should be discarded.
• Recommended values must be programmed and forbidden values must not be
programmed where they are indicated to avoid unexpected results.
8.6.1 TDC1011 Registers
Table 3 list the memory-mapped registers for the TDC1011. All register addresses not listed in Table 3 should be
considered as reserved locations and the register contents should not be modified.
Address (Hex)
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Table 3. TDC1011 REGISTERS
Acronym
CONFIG_0
CONFIG_1
CONFIG_2
CONFIG_3
CONFIG_4
TOF_1
TOF_0
ERROR_FLAGS
TIMEOUT
CLOCK_RATE
Register Name
Config-0
Config-1
Config-2
Config-3
Config-4
TOF-1
TOF-0
Error Flags
Timeout
Clock Rate
Reset Value
45h
40h
0h
3h
1Fh
0h
0h
0h
19h
0h
Section
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8.6.1.1 CONFIG_0 Register (address = 0h) [reset = 45h] (map)
Figure 41. CONFIG_0 Register
(MSB) 7
6
5
4
3
2
1
TX_FREQ_DIV
NUM_TX
R/W-2h
R/W-5h
LEGEND: R/W = Read or write; R = Read only; R/W1C = Read or write 1 to clear
0 (LSB)
Table 4. CONFIG_0 Register Field Descriptions
Bit Field
Type
Reset
Description
[7:5] TX_FREQ_DIV⁽¹⁾
R/W
2h
Frequency divider for TX clock and T1
0h: Divide by 2
1h: Divide by 4
2h: Divide by 8 (default)
3h: Divide by 16
4h: Divide by 32
5h: Divide by 64
6h: Divide by 128
7h: Divide by 256
[4:0] NUM_TX
R/W
5h
Number of TX pulses in a burst, ranging from 0 to 31.
5h: 5 pulses (default)
(1) See Timing Control and Frequency Scaling (CLKIN) for the definition of the time period T1.
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