TLFD600 Datasheet, PDF (5/37 Pages) Texas Instruments – ADSL CODEC WITH INTEGRATED LINE DRIVER AND RECEIVER

TLFD600
ADSL CODEC WITH INTEGRATED LINE DRIVER AND RECEIVER
SLAS280B – MAY 2000 – REVISED NOVEMBER 2000
TERMINAL
NAME
NO.
MODESEL
10
PLLSEL
26
PWRDWN
11
REFM
41
REFP
42
RESET
12
RXBANDGAP
43
RXINM
56
RXINP
55
SCLK
13
SDR
14
SDX
17
TXBANDGAP
7
TXOUTP
3
TXOUTM
4
VCXO_CNTL
47
VMID_ADC
40
VSS
48
detailed description
Terminal Functions (Continued)
I/O
DESCRIPTION
I Mode selection. MODESEL = 0 enable full rate mode. MODESEL = 1 enable G.lite mode. The default
state of this pin is low. The chip goes with the setting of the register programming, if the configuration
is different with this pin.
I DPLL mode selection. PLLSEL = 1 will enable DPLL mode. The default state of this pin is low.
I Power-down pin. When PWRDWN is pulled low, the device goes into power-down mode.
O Voltage reference filter negative output. There are two capacitors, with values of 10 µF and 0.1 µF,
connected in parallel to analog ground. The nominal dc voltage at this terminal is 0.5 V.
O Voltage reference filter positive output. There are two capacitors, with values of 10 µF and 0.1 µF,
connected in parallel to analog ground. The dc voltage at this terminal is 2.5 V.
I Device reset input pin. Initializes all of the device’s internal registers to their default values when
RESET is pulled low.
O RX channel bandgap filter node. This terminal is provided for decoupling of the 1.5-V band gap
reference. There are two capacitors, with values of 10 µF and 0.1 µF, connected in parallel to analog
ground. This node should not be used as a voltage source.
I RX channel stage negative input. This pin should not be directly connected. Refer to receive channel
for configuration.
I RX channel stage positive input. This pin should not be directly connected. Refer to receive channel
for configuration.
O Serial port shift clock (for both transmit and receive)
I Serial data receive
O Serial data transmit
O TX channel band gap filter node. This terminal is provided for decoupling of the 1.5-V band gap
reference. There are two capacitors, with values of 10 µF and 0.1 µF, connected in parallel to analog
ground. This node should not be used as a voltage source.
O TX channel positive output
O TX channel negative output
O DAC output to control off-chip VCXO
O Decoupling VMID for ADC. Add a 10-µF and a 0.1-µF capacitor between this pin and analog ground.
I Substrate. Connect to analog ground
transmit channel
The transmitter channel is powered by a high performance DAC. This is a 4.416 MHz, 14-bit DAC that provides
16X over-sampling to reduce the DAC noise. A band pass filter limits the output of the transmitter from 28.875
kHz to 138 kHz. A programmable attenuation with a range of 24 dB, in 1 dB step size, drives the output into the
on-chip ADSL line driver (ac-coupling is needed). The 25.875-kHz digital high pass filter (HPF) can be bypassed
by register programming.
The interface transfer rate is either 276 kHz or 552 kHz, controlled by register programming. The 138-kHz low
pass filter edge is programmable and is controlled by bit D4 of FMR register. D4=0 selects 138-kHz (±3.5%)
pole, while D4=1 selects a 125-kHz (±3.5%) pole. For details of register programming, see register
programming section.
The output spectrum of the DAC complies with the nonoverlapped PSD mask specified in the ITU standard
G.992.2 for G.lite application and G.992.1 for full rate application.
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