TLFD600 Datasheet, PDF (27/37 Pages) Texas Instruments – ADSL CODEC WITH INTEGRATED LINE DRIVER AND RECEIVER

TLFD600
ADSL CODEC WITH INTEGRATED LINE DRIVER AND RECEIVER
SLAS280B – MAY 2000 – REVISED NOVEMBER 2000
PROGRAMMING INFORMATION
equalizer shape control register
Address: 00101b
D7
D6
Reserved
Reserved
Contents at reset: 00000000b
D5
D4
D3
Reserved
Reserved
Reserved
D2
EQS[2]
D1
EQS[1]
D0
EQS[0]
Table 9. EQR Shape Table
BIT NAME
Reserved
D7 D6 D5 D4 D3 D2 D1 D0
0
Reserved
DESCRIPTION
Reserved
0
Reserved
Reserved
0
Reserved
Reserved
0
Reserved
Reserved
0
Reserved
EQS[2]
EQS[1]
EQS[0]
0
0
0 RX EQ = 0 dB/MHz
0
0
1 RX EQ = 5 dB/MHz
0
1
0 RX EQ = 10 dB/MHz
0
1
1 RX EQ = 15 dB/MHz
1
0
0 RX EQ = 20 dB/MHz
1
0
1 RX EQ = 25 dB/MHz
–
–
– See Note 6 for all other combinations
NOTE 6. Performance of the codec for invalid combination of bits is not guaranteed and such combinations should not be used.
VCR-M – VCXO DAC control register MSB
Address: 00110b
D7
D6
VCRMM[7]
VCRM[6]
Contents at reset: 00000000b
D5
D4
D3
VCRM[5]
VCRM[4]
VCRM[3]
D2
VCRM[2]
D1
VCRM[1]
D0
VCRM[0]
VCR-L – VCXO DAC control register LSB
Address: 00111b
D7
D6
0
0
Contents at reset: 00000000b
D5
D4
D3
0
0
VCRL[3]
D2
VCRL[2]
D1
VCRL[1]
D0
VCRL[0]
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