TLFD600 Datasheet, PDF (16/37 Pages) Texas Instruments – ADSL CODEC WITH INTEGRATED LINE DRIVER AND RECEIVER

TLFD600
ADSL CODEC WITH INTEGRATED LINE DRIVER AND RECEIVER
SLAS280B – MAY 2000 – REVISED NOVEMBER 2000
DPLL description (continued)
The position of the first jittering SCLK cycle is calculated by using the following equation:
) ) (NCO_DIV_DLY [7 : 0] 1) 16 7
The following jittering SCLKs will separate by 16 SCLK from the first one if NCO_DELTA[3:0] is more than one.
Figures 16 and 17 shows the timing of SCLK at the following setting:
NCO_DELTA [7:4] = – 1
NCO_DELTA [3:0] = 2
NCO_DIV_DELAY = 2
64 SCLKs
FSR
P
S
P
P
Start counting
FSX
P
P
P
P
P
P
P
P
P
P
16 SCLKs
SDR
Don’t care
Data
Don’t care
Data
Secondary Command Request
Command to Program
NCO_DIV_DELAY
15th 0
SCLK
The 9th SCLK duty cycle change
to 14ns(1) and 7ns(0)
Figure 16. DPLL Operation Example (FSR = 552 kHz and FSX = 2208 kHz)
NOTE: The situation will be the same for FSR = 276 kHz
16
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