TLFD600 Datasheet, PDF (24/37 Pages) Texas Instruments – ADSL CODEC WITH INTEGRATED LINE DRIVER AND RECEIVER

TLFD600
ADSL CODEC WITH INTEGRATED LINE DRIVER AND RECEIVER
SLAS280B – MAY 2000 – REVISED NOVEMBER 2000
PROGRAMMING INFORMATION
BCR – bypass control register
Address: 00001b
D7
D6
PDTXDR
DIG_LOW
Contents at reset: 00000000b
D5
D4
D3
DIG_HIGH
Reserved
ECHO
D2
BPTXHP
D1
Reserved
D0
Reserved
Table 5. BCR Control Table
BIT NAME
D7 D6 D5 D4 D3 D2 D1 D0
DESCRIPTION
PDTXDR
1
Power down TX line driver
DIG_LOW
1
Force all digital outputs low
DIG_HIGH
1
Force all digital outputs high
Reserved
0
Reserved bit. See Note 4
ECHO
1
Echo SDR data on SDX. See Note 5
BPTXHP
1
Bypass TX HP Filter (25.875 kHz)
Reserved
0
Reserved
Reserved
0 Reserved
NOTES: 4. All reserved bits should be programmed as 0 during normal application.
5. ECHO mode allows for a quick verification of whether the TLFD600 serial interface is working. It sends back the data from the input
data buffer to the output data buffer and does not go through the RX or TX channel.
PCR-RX1 – programmable gain control register 1 for RX channel
Address: 00010b
D7
D6
Reserved
Reserved
Contents at reset: 00000000b
D5
D4
D3
RXPGA3[3]
RXPGA3[2]
RXPGA3[1]
D2
RXPGA3[0]
D1
Reserved
D0
Reserved
Table 6. PCR-RX1 Gain Table
BIT NAME
Reserved
D7 D6 D5 D4 D3 D2 D1 D0
0
Reserved
DESCRIPTION
Reserved
0
Reserved
RXPGA3[3]
RXPGA3[2]
RXPGA3[1]
RXPGA3[0]
0
0
0
0
RX PGA3 = 0 dB
0
0
0
1
RX PGA3 = 1 dB
0
0
1
0
RX PGA3 = 2 dB
0
0
1
1
RX PGA3 = 3 dB
0
1
0
0
RX PGA3 = 4 dB
0
1
0
1
RX PGA3 = 5 dB
0
1
1
0
RX PGA3 = 6 dB
0
1
1
1
RX PGA3 = 7 dB
1
0
0
0
RX PGA3 = 8 dB
1
0
0
1
RX PGA3 = 9 dB
–
–
–
–
See Note 6 for all other combinations
Reserved
0
Reserved
Reserved
0 Reserved
NOTE 6: Performance of the codec for invalid combination of bits is not guaranteed and such combinations should not be used.
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