TLFD600 Datasheet, PDF (18/37 Pages) Texas Instruments – ADSL CODEC WITH INTEGRATED LINE DRIVER AND RECEIVER

TLFD600
ADSL CODEC WITH INTEGRATED LINE DRIVER AND RECEIVER
SLAS280B – MAY 2000 – REVISED NOVEMBER 2000
register programming
The codec registers are listed below. All registers are 8-bits wide. Bits not defined in Table 4 are reserved for
future use. These reserved bits need to be written as zero during register programming.
Table 4. Register Programming
REGISTER
NAME
ADDRESS
A4–A0
DEFAULT
VALUE
FUNCTION
BCR
00001
00000000
D2: Bypass TX digital HP filter
D3: Echo mode: Echo SDR data on SDX
D5: Force all digital outputs high
D6: Force all digital outputs low
D7: Power-down TX line driver
PCR-RX1
00010
00000000 D[5:2] = RXPGA3[3:0]; Fine gain, 0 to 9 dB, 1 dB step
PCR-RX2
00011
00001011
D[7:4] = RXPGA2[3:0]; 0 to 30 dB, 3 dB step
D[3:0] = RXCPGA[3:0]; – 9 to 9 dB at 6 dB/step and 9 to 30 dB at 3 dB/step.
PCR-TX
00100
00000000 D[4:0] = TX PAA[4:0]; 0 to – 24 dB, – 1 dB/step
EQR
00101
00000000 D[2:0] = EQ[2:0]; 0 to 25 dB/MHz, 5 dB/MHz per step
VCR-M
00110
00000000 D[7:0] = VCXO DAC control Bit[11:4]
VCR-L
00111
00000000 D[3:0] = VCXO DAC control Bit[3:0]. D[7:4] must be zero
NOT USED
01000
00000000 Reserved
GPR-D
01001
00000000 D[7:0] = General-purpose I/O data register data
FMR
01010
00000000
D0: G.Lite/full rate mode selection. (0 = same as pin default, 1 = opposite of pin
default. See MODESEL in pin description section)
D1:TX update rate selection; 276 Ksps (D1 = 0) or 512 Ksps (D1=1)
D2:Reserved
D3:Reserved
D4:Bandwidth selection for TX channel (0 = 138 kHz, 1 = 125 kHz)
AUXGPRC
01011
00001100
D0=1: Enable auxiliary amplifier 2
D1=1: Enable auxiliary amplifier 1
D[3:2] = GPIO0 and GPIO1 I/O control (0 = output, 1 = input)
NCO_DEF
01100
01000000 D[6:0] = Default NCO divide number
NCO_DIV_DLY
01101
00000000
D[7:0] Number of samples (or frames), from current secondary transfer, after which
effect of delta will occur. This register should be the last register to be programmed
in DPLL mode.
NCO_DELTA
01110
00000000
D[7:4] = Delta from default for first sample of data frame (– 1 through 1)
D[3:0] = Number of times the internal NCO divider remains changed after register
NCO_DIV_DLY is programmed.
MCR
01111
00000000
D0: S/W power down main reference
D1: S/W power down TX channel with reference still on
D2: S/W power down RX channel with reference still on
D3: S/W power down VCXO DAC with reference still on
D4: S/W reset
D5: Analog loop back
D6: Digital loop back
D7: Enable GPIO0 and 1 to show in SDX primary data.
NOTE: The gain range of CPGA is related to the external resistor. The gain setting shown above is under the condition of R = 732 Ω and
C = 680 pF. Refer to the receiver channel section for details.
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