TLFD600 Datasheet, PDF (31/37 Pages) Texas Instruments – ADSL CODEC WITH INTEGRATED LINE DRIVER AND RECEIVER

TLFD600
ADSL CODEC WITH INTEGRATED LINE DRIVER AND RECEIVER
SLAS280B – MAY 2000 – REVISED NOVEMBER 2000
PROGRAMMING INFORMATION
MCR – master control register
Address: 01111b
D7
D6
GP12EN
DLBEN
Contents at reset: 00000000b
D5
D4
D3
ALBEN
SWRST
VCDACPD
D2
RXPD
D1
TXPD
D0
SWREFPD
Table 16. MCR Control Table
BIT NAME
GP12EN
D7 D6 D5 D4 D3 D2 D1 D0
DESCRIPTION
1
Show GPIO 1, 2 in SDX primary
DLBEN
1
Enable digital loop back
ALBEN
1
Enable analog loop back
SWRST
1
Software reset
VCDACPD
1
Power down VCXO DAC
RXPD
1
Power down RX channel
TXPD
1
Power down TX channel
SWREFPD
1 Power down main reference
NOTES: 12. Analog loop back means looping back of the analog TX output to the RX input (the RX high-pass filters are bypassed). This way
the codec can be tested without needing external analog sources. Refer to block diagram for signal path.
13. Digital loop back means looping back the digital RX output to the TX input. Refer to block diagram for signal path.
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