TLFD600 Datasheet, PDF (3/37 Pages) Texas Instruments – ADSL CODEC WITH INTEGRATED LINE DRIVER AND RECEIVER

functional block diagram
TLFD600
ADSL CODEC WITH INTEGRATED LINE DRIVER AND RECEIVER
SLAS280B – MAY 2000 – REVISED NOVEMBER 2000
25.875 kHz
276 Ksps/
552 Ksps
Digital
HPF
138 kHz
Digital
LPF
14 Bit
4.416 Msps
TX DAC
138 kHz
TX
LPF
0 to –24 dB
(–1 dB/Step)
TX PGA
PAA
TXOUTP/
TXOUTM
FSR
FSX
SDR
SDX
SCLK
Digital Loopback
552 kHz/
1104 kHz
RX
1104 Ksps/ ^LPF
2208 Ksps
14 Bit
4.416 Msps
ADC
0 to 9 dB
(1 dB/Step)
RX PGA3
PGA
Analog Loopback
552 kHz/
1104 kHz
LPF
LD
TX Line Driver
DRIVERINP/
DRIVERINM
DRIVEROUTP/
DRIVEROUTM
180 kHz
Equalizer
PGA
HPF
PGA
180 kHz
HPF
RXINP/
RXINM
0 to 25 dB/MHz
5 dB/MHz Step
0 to 30 dB
(3 dB/Step)
RX PGA2
Internal Clock
–9 to +9 dB @ 6 dB/Step
+9 to 30 dB @ 3 dB/Step
RX CPGA (See Note)
AUX
Amplifiers (2)
AMPOUTP/
AMPOUTM
DPLL
AMPINP/
AMPINM
VCXO
DAC
Clock Generator
Internal Reference
General
Purpose I/O
GPO2-GPO5
GPIO0-GPIO1
VCXO MCLKIN
VCXO
35.328 MHz
CLK1OUT/
CLK2OUT
CLK1SEL/
CLKOUT_EN
VMID_ADC
PLLSEL
REFM/REFP
TXBANDGAP/
RXBANDGAP
NOTE: The CPGA gain range setting is related to the external components (R and C) that are connected to RXINP/M. Refer to the receiver channel
section for details.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3