TLFD600 Datasheet, PDF (4/37 Pages) Texas Instruments – ADSL CODEC WITH INTEGRATED LINE DRIVER AND RECEIVER

TLFD600
ADSL CODEC WITH INTEGRATED LINE DRIVER AND RECEIVER
SLAS280B – MAY 2000 – REVISED NOVEMBER 2000
TERMINAL
NAME
NO.
AMP1INM
50
AMP2INM
59
AMP1INP
51
AMP2INP
58
AMP1OUTM
52
AMP2OUTM
57
AMP1OUTP
49
AMP2OUTP
60
ANA_TST
46
AVDD_DRIVER
AVDD_REF
AVDD_RX
AVDD_TX
AVSS_DRIVER
AVSS_REF
AVSS_RX
AVSS_TX
CLK1OUT
CLK2OUT
CLK1SEL
CLKOUT_EN
63
45
38, 53
5
61
44
39, 54
6
27
28
20
21
COMPDAC1
COMPDAC2
DRIVERINM
DRIVERINP
DRIVEROUTM
DRIVEROUTP
DVDD
DVDD_IO
DVDD_RX
DVSS
DVSS_IO
DVSS_RX
FSX
FSR
GPIO0
GPIO1
GPO2 – 5
MCLKIN/PLLCLKIN
8
9
2
1
62
64
22
18
30
23, 24, 37
19
31
16
15
29
32
33 – 36
25
Terminal Functions
I/O
DESCRIPTION
I Auxiliary amplifier 1 and 2 negative input
I Auxiliary amplifier 1 and 2 positive input
O Auxiliary amplifier 1 and 2 negative output
O Auxiliary amplifier 1 and 2 positive output
I External resistor connection input. A 15-kΩ (±5%) resistor must be connected between
ANA_TST and analog ground.
I Analog power supply for TX driver (12 V)
I Reference analog supply
I RX channel filter analog supply
I TX channel analog supply
I TX driver analog supply return (analog ground)
I Reference analog supply return (analog ground)
I RX channel filter analog supply return (analog ground)
I TX channel analog supply return (analog ground).
O Generates clock of frequency MCLKx4/n, where n is 7 or 9. Value of n is selected by CLK1SEL.
O Generates clock of frequency MCLKx4/34.5.
I Selects whether n = 7 or 9 for CLK1OUT. For CLK1SEL = 0, n = 6.
I Enable CLK1OUT and CLK2OUT when CLKOUT_EN is high. The default state of
CLKOUT_EN is low.
I TX channel decoupling cap input A. Add a 1-µF ceramic capacitor to analog power supply.
I TX channel decoupling cap input B. Add a 1-µF ceramic capacitor to analog power supply.
I TX channel driver negative input. A 0.1-µF capacitor is needed when it connects to TXOUTM.
I TX channel driver positive input. A 0.1-µF capacitor is needed when it connects to TXOUTP.
O TX channel driver negative output
O TX channel driver positive output
I Digital power supply
I Power supply for digital I/O buffer
I RX channel digital power supply
I Digital ground
I Digital I/O buffer supply return (digital ground)
I RX channel digital supply return (digital ground)
O Serial port frame sync transmit signal
O Serial port frame sync receive signal
I/O General-purpose I/O
O General-purpose output
I Master clock input for normal mode (use off-chip VCXO) and DPLL (use fix input clock and
change clock phase by control register) mode. The required input clock frequency is
35.328 MHz ± 50 ppm.
4
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265