BQ24296_15 Datasheet, PDF (5/55 Pages) Texas Instruments – bq2429x I2C Controlled 3-A Single Cell USB Charger With Narrow VDC Power Path Management and Adjustable Voltage USB OTG

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bq24296, bq24297
SLUSBP6B – SEPTEMBER 2013 – REVISED NOVEMBER 2014
bq24296
ILIM
PIN
bq24297
ILIM
TS
QON
TS
QON
BAT
SYS
PGND
BAT
SYS
PGND
SW
SW
BTST
REGN
BTST
REGN
PMID
PMID
Thermal Pad Thermal Pad
NUMBER
TYPE
Pin Functions (continued)
DESCRIPTION
10
11
12
13,14
15,16
17,18
19,20
21
22
23
–
I ILIM pin sets the maximum input current limit by regulating the ILIM voltage at 1 V. A resistor is
connected from ILIM pin to ground to set the maximum limit as I_INMAX = (1V/R_ILIM) × K_ILIM. The actual
input current limit is the lower one set by ILIM and by I²C REG00[2:0]. The minimum input current
programmed on ILIM pin is 500 mA.
I Temperature qualification voltage input. Connect a negative temperature coefficient thermistor. Program
Analo ^{temperature window with a resistor divider from REGN to TS to GND. Charge suspends or Boost}
g ^{disable when TS pin is out of range. A 103AT-2 thermistor is recommended.}
I BATFET enable control in shipping mode. A logic low to high transition on this pin with minimum 2-ms
high level turns on BATFET to exit shipping mode. It has internal 1-MΩ (Typ) pull down. For backward
compatibility, when BATFET enable control function is not used, the pin can be no connect or tied to TS
pin (10-kΩ NTC thermister only). (Refer to Shipping Mode for detail description).
P Battery connection point to the positive pin of the battery pack. The internal BATFET is connected
between BAT and SYS. Connect a 10 µF closely to the BAT pin.
I System connection point. The internal BATFET is connected between BAT and SYS. When the battery
falls below the minimum system voltage, switch-mode converter keeps SYS above the minimum system
voltage.
P Power ground connection for high-current power converter node. Internally, PGND is connected to the
source of the n-channel LSFET. On PCB layout, connect directly to ground connection of input and
output capacitors of the charger. A single point connection is recommended between power PGND and
the analog GND near the IC PGND pin.
O Switching node connecting to output inductor. Internally SW is connected to the source of the n-channel
HSFET and the drain of the n-channel LSFET. Connect the 0.047-µF bootstrap capacitor from SW to
BTST.
P PWM high side driver positive supply. Internally, the BTST is connected to the anode of the boost-strap
diode. Connect the 0.047-µF bootstrap capacitor from SW to BTST.
P PWM low side driver positive supply output. Internally, REGN is connected to the cathode of the boost-
strap diode. Connect a 4.7-µF (10-V rating) ceramic capacitor from REGN to analog GND. The
capacitor should be placed close to the IC. REGN also serves as bias rail of TS pin.
O Connected to the drain of the reverse blocking MOSFET and the drain of HSFET. Given the total input
capacitance, connect a 1-µF capacitor on VBUS to PGND, and the recommended 8.2 µF or more on
PMID to PGND.
P Exposed pad beneath the IC for heat dissipation. Always solder thermal pad to the board, and have vias
on the thermal pad plane star-connecting to PGND and ground plane for high-current power converter.
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