BQ24296_15 Datasheet, PDF (31/55 Pages) Texas Instruments – bq2429x I2C Controlled 3-A Single Cell USB Charger With Narrow VDC Power Path Management and Adjustable Voltage USB OTG

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Programming (continued)
SDA
MSB
Acknowledgement
signal from slave
bq24296, bq24297
SLUSBP6B – SEPTEMBER 2013 – REVISED NOVEMBER 2014
Acknowledgement
signal from receiver
SCL
S or Sr
START or
Repeated
START
1
2
7
8
9
ACK
1
2
Figure 23. Data Transfer on the I²C Bus
8
9
ACK
P or Sr
STOP or
Repeated
START
9.5.1.4 Acknowledge (ACK) and Not Acknowledge (NACK)
The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter
that the byte was successfully received and another byte may be sent. All clock pulses, including the
acknowledge 9^th clock pulse, are generated by the master.
The transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line
LOW and it remains stable LOW during the HIGH period of this clock pulse.
When SDA remains HIGH during the 9th clock pulse, this is the Not Acknowledge signal. The master can then
generate either a STOP to abort the transfer or a repeated START to start a new transfer.
9.5.1.5 Slave Address and Data Direction Bit
After the START, a slave address is sent. This address is 7 bits long followed by the eighth bit as a data direction
bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ).
SDA
SCL
S
START
1-7
ADDRESS
8
9
1-7
8
9
R/W ACK
DATA
ACK
Figure 24. Complete Data Transfer
1-7
8
DATA
9
ACK
P
STOP
9.5.1.5.1 Single Read and Write
1
7
1
1
S Slave Address 0 ACK
8
Reg Addr
1
ACK
8
Data Addr
1
1
ACK P
Figure 25. Single Write
1
7
1
1
S Slave Address 0 ACK
8
Reg Addr
1
1
7
1
1
ACK S Slave Address 1 ACK
8
Data
1
1
NCK P
Figure 26. Single Read
If the register address is not defined, the charger IC send back NACK and go back to the idle state.
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