BQ24296_15 Datasheet, PDF (45/55 Pages) Texas Instruments – bq2429x I2C Controlled 3-A Single Cell USB Charger With Narrow VDC Power Path Management and Adjustable Voltage USB OTG

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bq24296, bq24297
SLUSBP6B – SEPTEMBER 2013 – REVISED NOVEMBER 2014
11 Power Supply Recommendations
In order to provide an output voltage on SYS, the bq24296/297 require a power supply between 3.9 V and 6.2 V
input with at least 100-mA current rating connected to V_BUS; or, a single-cell Li-Ion battery with voltage >
V_BATUVLO connected to BAT. The source current rating needs to be at least 3 A in order for the buck converter of
the charger to provide maximum output power to SYS.
12 Layout
12.1 Layout Guidelines
The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the
components to minimize high frequency current path loop (see Figure 53) is important to prevent electrical and
magnetic field radiation and high frequency resonant problems. Here is a PCB layout priority list for proper
layout. Layout PCB according to this specific order is essential.
1. Place input capacitor as close as possible to PMID pin and GND pin connections and use shortest copper
trace connection or GND plane.
2. Place inductor input pin to SW pin as close as possible. Minimize the copper area of this trace to lower
electrical and magnetic field radiation but make the trace wide enough to carry the charging current. Do not
use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any other
trace or plane.
3. Put output capacitor near to the inductor and the IC. Ground connections need to be tied to the IC ground
with a short copper trace connection or GND plane.
4. Route analog ground separately from power ground. Connect analog ground and connect power ground
separately. Connect analog ground and power ground together using thermal pad as the single ground
connection point. Or using a 0Ω resistor to tie analog ground to power ground.
5. Use single ground connection to tie charger power ground to charger analog ground. Just beneath the IC.
Use ground copper pour but avoid power pins to reduce inductive and capacitive noise coupling.
6. Decoupling capacitors should be placed next to the IC pins and make trace connection as short as possible.
7. It is critical that the exposed thermal pad on the backside of the IC package be soldered to the PCB ground.
Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the
other layers.
8. The via size and number should be enough for a given current path.
See the EVM design for the recommended component placement with trace and via locations. For the VQFN
information, refer to SCBA017 and SLUA271.
Figure 53. High Frequency Current Path
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