BQ24296_15 Datasheet, PDF (19/55 Pages) Texas Instruments – bq2429x I2C Controlled 3-A Single Cell USB Charger With Narrow VDC Power Path Management and Adjustable Voltage USB OTG

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bq24296, bq24297
SLUSBP6B – SEPTEMBER 2013 – REVISED NOVEMBER 2014
When DCD 0.5 sec timer expires, the non-standard adapter detection is used to distinguish three different divider
bias conditions on D+/D- pins. When non-standard adapter is detected, the input current limit (REG0[2:0]) is set
based on the table shown below and REG08[7:6] is set to 10 (Adapter port). If non-standard adapter is not
detected, REG08[7:6] is set to 00 (Unknown) and the input current limit is set in REG0[2:0] to 500 mA by default.
NON-
STANDARD
ADAPTER
Divider 1
Divider 2
Divider 3
Table 3. bq24297 Non-Standard Adapter Detection
D+ THRESHOLD
D- THRESHOLD
V_{adpt1_lo} < V_D+ < V_{adpt1_hi}
For VBUS = 5 V, typical range 2.4 V < V_D+ < 3.1 V
V_{adpt2_lo} < V_D+ < V_{adpt2_hi}
For VBUS = 5 V, typical range 0.85 V < V_D+ < 1.5 V
V_D+< V_{adpt3_lo} or V_D+> V_{adpt3_hi}
For VBUS = 5 V, typical range V_D+ < 2.4 V or V_D+ >
3.1 V
V_D- < V_{adpt1_lo} or V_D- > V_{adpt1_hi}
For VBUS = 5 V, typical range V_D- < 2.4 V or V_D- >
3.1 V
NA
V_{adpt3_lo} < V_D- < V_{adpt3_hi}
For VBUS = 5 V, typical range 2.4 V < V_D- < 3.1 V
INPUT
CURRENT
LIMIT
2.0A
2.0A
1A
After D+/D- detection is completed with an input source already plugged in, the input current limit is not changed
unless DPDM_EN (REG07[7]) bit is set to force detection.
9.3.1.3.5 PSEL/OTG Pins Set Input Current Limit
The bq24296 has PSEL instead of D+/D-. It directly takes the USB PHY device output to decide whether the
input is USB host or charging port.
PSEL
HIGH
HIGH
LOW
Table 4. bq24296 Input Current Limit Detection
OTG
LOW
HIGH
—
INPUT CURRENT LIMIT
100 mA
500 mA
3A
REG08[7:6]
01
01
10
9.3.1.3.6 HIZ State with 100mA USB Host
In battery charging spec, the good battery threshold is the minimum charge level of a battery to power up the
portable device successfully. When the input source is 100-mA USB host, and the battery is above bat-good
threshold (V_BATGD), the device follows battery charging spec and enters high impedance state (HIZ). In HIZ state,
the device is in the lowest quiescent state with REGN LDO and the bias circuits off. The charger device sets
REG00[7] to 1, and the VBUS current during HIZ state will be less than 30 µA. The system is supplied by the
battery.
Once the charger device enters HIZ state in host mode, it stays in HIZ until the host writes REG00[7] = 0. When
the processor host wakes up, it is recommended to first check if the charger is in HIZ state.
In default mode, the charger IC will reset REG00[7] back to 0 when input source is removed. When another
source plugs in, the charger IC will run detection again, and update the input current limit.
9.3.1.3.7 Force Input Current Limit Detection
While adapter is plugged-in, the host can force the charger device to run input current limit detection by setting
REG07[7] = 1 or when watchdog timeout. During the forced detection, the input current limit is set to 100 mA.
After the detection is completed, REG07[7] will return to 0 by itself and new input current limit is set based on
D+/D- (bq24297) or PSEL/OTG (bq24296).
9.3.1.4 Converter Power-Up
After the input current limit is set, the converter is enabled and the HSFET and LSFET start switching. If battery
charging is disabled, BATFET turns off. Otherwise, BATFET stays on to charge the battery.
The device provides soft-start when ramp up the system rail. When the system rail is below 2.2 V, the input
current limit is forced to 100mA. After the system rises above 2.2 V, the charger device sets the input current
limit set by the lower value between register and ILIM pin.
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