BQ24296_15 Datasheet, PDF (10/55 Pages) Texas Instruments – bq2429x I2C Controlled 3-A Single Cell USB Charger With Narrow VDC Power Path Management and Adjustable Voltage USB OTG

bq24296, bq24297
SLUSBP6B – SEPTEMBER 2013 – REVISED NOVEMBER 2014
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Electrical Characteristics (continued)
V_{VBUS_UVLOZ} < V_VBUS < V_ACOV and V_VBUS > V_BAT + V_SLEEP, T_J = –40°C to 125°C and T_J = 25°C for typical values unless other
noted.
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
VBHOT2
Hot temperature threshold 2, TS pin
voltage falling threshold
As percentage to V_REGN REG06[3:2] = 10
(Approx. 65°C w/ 103AT)
29.5% 30% 30.5%
VBHOT2_HYS
As percentage to V_REGN REG06[3:2] = 10
(Approx. 3°C w/ 103AT)
3%
CHARGE OVER-CURRENT COMPARATOR
I_{HSFET_OCP}
HSFET cycle by cycle over-current
threshold
5.3
7.5
A
I_{BATFET_OCP}
V_{LSFET_UCP}
System over load threshold
LSFET charge under-current falling
threshold
From sync mode to non-sync mode
5.5
6.6
A
100
mA
F_SW
PWM Switching frequency, and digital
clock
1300 1500 1700 kHz
D_MAX
V_{BTST_REFRESH}
Maximum PWM duty cycle
Bootstrap refresh comparator threshold
VBTST-VSW when LSFET refresh pulse is requested,
VBUS = 5 V
97%
3.6
V
BOOST MODE OPERATION
V_{OTG_REG_ACC}
V_{OTG_REG_ACC}
V_{OTG_BAT}
I_OTG
OTG output voltage
OTG output voltage accuracy
Battery voltage exiting OTG mode
OTG mode output current
I(VBUS) = 0, REG06[7:4] = 0111 (4.998 V)
I(VBUS) = 0, REG06[7:4] = 0111 (4.998 V)
BAT falling, REG04[1] = 1
REG01[0] = 0
REG01[0] = 1
5
V
-3%
3%
2.9
V
1
A
1.5
A
V_{OTG_OVP}
V_{OTG_OVP_HYS}
I_{OTG_LSOCP}
I_{OTG_HSZCP}
I_{RBFET_OCP}
OTG over-voltage threshold
OTG over-voltage threshold hysteresis
LSFET cycle by cycle current limit
HSFET under current falling threshold
RBFET over-current threshold
Rising threshold
Falling threshold
REG01[0] = 0
REG01[0] = 1
5.8
6
V
300
mV
5
A
100
mA
1.00 1.15 1.30
A
1.50 1.70 1.90
REGN LDO
V_REGN
REGN LDO output voltage
V_VBUS = 6 V, I_REGN = 40 mA
V_VBUS = 5 V, I_REGN = 20 mA
I_REGN
REGN LDO current limit
V_VBUS = 5 V, V_REGN = 3.8 V
LOGIC I/O PIN CHARACTERISTICS (OTG, CE, STAT, QON, PSEL, PG)
4.8
5
5.5 V
4.7
4.8
V
50
mA
V_ILO
Input low threshold
V_IH
Input high threshold (CE, STAT, QON,
PSEL, PG)
0.4 V
1.3
V
V_{IH_OTG}
V_{OUT_LO}
I_BIAS
Input high threshold (OTG)
Output low saturation voltage
High level leakage current (OTG, CE,
STAT , PSEL, PG)
Sink current = 5 mA
Pull-up rail 1.8 V
1.1
V
0.4 V
1 µA
I_BIAS
High level leakage current (QON)
I²C INTERFACE (SDA, SCL, INT)
Pull-up rail 3.6 V
8 µA
V_IH
Input high threshold level
V_IL
Input low threshold level
V_OL
Output low threshold level
I_BIAS
High-level leakage current
f_SCL
SCL clock frequency
DIGITAL CLOCK AND WATCHDOG TIMER
VPULL-UP = 1.8 V, SDA and SCL
VPULL-UP = 1.8 V, SDA and SCL
Sink current = 5 mA
VPULL-UP = 1.8 V, SDA and SCL
1.3
V
0.4 V
0.4 V
1 µA
400 kHz
f_HIZ
Digital crude clock
f_DIG
Digital clock
REGN LDO disabled
REGN LDO enabled
15
1300
35
1500
50 kHz
1700 kHz
10
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