TLC32047C Datasheet, PDF (45/61 Pages) Texas Instruments – Wide-Band Analog Interface Circuit

SHIFT
CLK
2V
td _(CH-FL)
FSR,
8V
FSX
t _{f (SCLK)}
2V
DR
D15
D14
tsu _(DX)
DX
D15 D14
EODR,
EODX
t _{r (SCLK)}
td _(CH-DR)
D13
D9
td _(CH-FH)
2V
D8
D13 D9
th _(DX)
D8
8V
Don’t Care
td _(CH-EL)
2V
8V
2V
td _(CH-FL)
D7 D6
tc _(SCLK)
2V
2V
td _(CH-FH)
2V
D2
D1 D0
D12 D11 D2 D1
D0
td _(CH-EH)
2V
Figure 4–4. Byte-Mode Timing
†The time between falling edges of FSR is the A/D conversion period, and the time between fallling edges of FSX is the D/A conversion period.
‡ ^{In the byte mode, when EODX or EODR is high, the first byte is transmitted or received, and when these signals are low, the second byte is}
transmitted or received. Each byte-cycle is 12 shift-clocks long, allowing for a four-shift-clock setup time between byte transmissions.