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TLC32047C Datasheet, PDF (21/61 Pages) Texas Instruments – Wide-Band Analog Interface Circuit | |||
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XTAL
OSC
20.736 MHZ
41.472 MHZ
TMS320 DSP
5.184 MHz
MASTER CLOCK 10.368 MHz
Divide By 4
SHIFT CLOCK
1.296 MHz
2.592 MHz
Transmit Section
D/A Conversion
Timing
TA Register
(5 Bits)
See Table 2-3
TAâ² REGISTER
(6 Bits)
2s-Complement TA
See Table 2-3
Adder/Subtractor
â D1 D0 SELECT
0 0 TA
0 1 TA + TAâ²
1 0 TA â TAâ²
1 1 TA
6
See Table 2-2
12
TB Register
(6 Bits)
See Table 2-3
TX (A) Counter
Divide By 2
TX (B) Counter
(6 Bits)
864 kHz
432 kHz
SCF CLOCK
Low-Pass Filter,
(sin x)/x Filter
7.20 kHz for TB = 60
8.00 kHz for TB = 54
9.60 kHz for TB = 45
14.4 kHz for TB = 30
16.0 kHz for TB = 27
24.0 kHz for TB = 18
D/A Conversion
Frequency
Receive Section
A/D Conversion
Timing
RA Register
(5 Bits)
See Table 2-3
RAâ² Register
(6 Bits)
2s-Complement RA
See Table 2-3
Adder/Subtractor
â D1 D0 SELECT
0 0 RA
0 1 RA + RAâ²
1 0 RA â RAâ²
1 1 RA
6
12
See Table 2-2
RB Register
(6 Bits)
See Table 2-3
RX (A) Counter
(6 Bits)
Divide By 2
RX (B) Counter
864 kHz
432 kHz
SCF CLOCK
Low-Pass Filter
7.20 kHz for RB = 60
8.00 kHz for RB = 54
9.60 kHz for RB = 45
14.4 kHz for RB = 30
16.0 kHz for RB = 27
24.0 kHz for RB = 18
High-Pass Filter,
A/D Conversion
Frequency
â These control bits are described in the DX Serial Data Word Format section.
NOTES: A. Tables 2â2 and 2â3 (pages 2â9 and 2â10) are primary and secondary communication protocols,
respectively.
B. In synchronous operation, RA, RAâ, RB, RX(A), and RX(B) are not used. TA, TAâ, TB, TX(A), and TX(B) are
used instead.
C. Items in italics refer only to frequencies and register contents, which are variable. A crystal oscillator driving
20.736 MHz into the TMS320-series DSP provides a master clock frequency of 5.184 MHz. The TLC32047
produces a shift clock frequency of 1.296 MHz. If the TX(A) register contents equal 6, the SCF clock
frequency is then 432 kHz, and the D/A conversion frequency is 432 kHz ÷ T(B).
Figure 2â1. Asynchronous Internal Timing Configuration
2â3
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