TLC32047C Datasheet, PDF (41/61 Pages) Texas Instruments – Wide-Band Analog Interface Circuit

3.5 Timing Requirements
3.5.1 Serial Port Recommended Input Signals
PARAMETER
MIN
MAX UNIT
tc(MCLK)
tr(MCLK)
tf(MCLK)
Master clock cycle time
Master clock rise time
Master clock fall time
Master clock duty cycle
95
25%
ns
10 ns
10 ns
75%
RESET pulse duration (see Note 11)
800
ns
tsu(DX)
DX setup time before SCLK↓
20
ns
th(DX)
DX hold time after SCLK↓
tc(SCLK)/4
ns
NOTE 11: RESET pulse duration is the amount of time that the reset pin is held below 0.8 V after the power supplies have
reached their recommended values.
3.5.2
Serial Port – AIC Output Signals, C_L = 30 pF for SHIFT CLK Output, C_L = 15 pF
For All Other Outputs
PARAMETER
MIN TYP† MAX UNIT
tc(SCLK)
tf(SCLK)
tr(SCLK)
Shift clock (SCLK) cycle time
Shift clock (SCLK) fall time
Shift clock (SCLK) rise time
Shift clock (SCLK) duty cycle
380
ns
3
8 ns
3
8 ns
45
55 %
td(CH-FL) Delay from SCLK↑ to FSR/FSX/FSD↓
td(CH-FH) Delay from SCLK↑ to FSR/FSX/FSD↑
td(CH-DR) DR valid after SCLK↑
td(CH-EL) Delay from SCLK↑ to EODX/EODR↓ in word mode
td(CH-EH) Delay from SCLK↑ to EODX/EODR↑ in word mode
tf(EODX) EODX fall time
tf(EODR) EODR fall time
td(CH-EL) Delay from SCLK↑ to EODX/EODR↓ in byte mode
td(CH-EH) Delay from SCLK↑ to EODX/EODR↑ in byte mode
td(MH-SL) Delay from MSTR CLK↑ to SCLK↓
td(MH-SH) Delay from MSTR CLK↑ to SCLK↑
† _{Typical values are at TA = 25°C.}
30
ns
35
90 ns
90 ns
90 ns
90 ns
2
8 ns
2
8 ns
90 ns
90 ns
65 170 ns
65 170 ns
3–7