TLC32047C Datasheet, PDF (17/61 Pages) Texas Instruments – Wide-Band Analog Interface Circuit

1.5 Terminal Functions (continued)
TERMINAL
I/O
NAME
NO.
DESCRIPTION
RESET
2
I Reset. A reset function is provided to initialize TA, TA’, TB, RA, RA’, RB (see Figure 2-1),
and the control registers. This reset function initiates serial communications between
the AIC and DSP. The reset function initializes all AIC registers, including the control
register. After a negative-going pulse on RESET, the AIC registers are initialized to
provide a 16-kHz data conversion rate for a 10.368-MHz master clock input signal. The
conversion rate adjust registers, TA’ and RA’, are reset to 1. The CONTROL register bits
are reset as follows (see AIC DX Data Word Format section):
D11 = 0, D10 = 0, D9 = 1, D7 = 1, D6 = 1, D5 = 1, D4 = 0, D3 = 0, D2 = 1
The shift clock (SCLK) is held high during RESET.
This initialization allows normal serial-port communication to occur between the AIC
and the DSP.
SHIFT CLK
10 O Shift clock. SHIFT CLK is obtained by dividing the master clock signal frequency by four.
SHIFT CLK is used to clock the serial data transfers of the AIC.
VDD
VCC+
VCC _–
7
Digital supply voltage, 5 V ± 5%
20
Positive analog supply voltage, 5 V ± 5%
19
Negative analog supply voltage, – 5 V ± 5%
1–9