TLC32047C Datasheet, PDF (12/61 Pages) Texas Instruments – Wide-Band Analog Interface Circuit

FRAME SYNCHRONIZATION FUNCTIONS
TLC32047 Function
Receiving serial data on DX from processor to internal DAC
Transmitting serial data on DR from internal ADC to processor, primary communications
Transmitting serial data on DR from DATA-DR to processor, secondary communications in
dual-word (telephone interface) mode only
Frame Sync Output
FSX low
FSR low
FSD low
Analog In
Analog Out
5V
–5 V
20
19
26
VCC ₊
IN +
VCC _–
Serial Data Out
DR ⁵
25
IN –
TLC32047
4
FSR
3
D11OUT
22
OUT +
21
OUT –
12 Serial Data In
DX
FSX ¹⁴
11
D10OUT
TMS32020,
TMS320C25,
TMS320C30,
or Equivalent
16-Bit DSP
TTL or CMOS
Logic Levels
1
FSD
DATA-DR
Secondary Communication (see Table above)
13 Serial Data Input
16-Bit Format TTL
or CMOS Logic Levels
Figure 1–1. Dual-Word (Telephone Interface) Mode
When the DATA-DR/CONTROL input is tied to a logic signal source varying between 0 and 5 V, the
TLC32047 is in the dual-word (telephone interface) mode. This logic signal is routed to the DR line for input
to the DSP only when terminal 1, data frame synchronization (FSD), outputs a low level. The FSD pulse
duration is 16 shift clock pulses. Also, in this mode, the control register data bits D10 and D11 appear on
D10OUT and D11OUT, respectively, as outputs.
1–4