TLC32047C Datasheet, PDF (30/61 Pages) Texas Instruments – Wide-Band Analog Interface Circuit

Table 2–4. AIC Responses to Improper Conditions
IMPROPER CONDITION
TA register + TA′ register = 0 or 1
TA register – TA′ register = 0 or 1
AIC RESPONSE
Reprogram TX(A) counter with TA register value
TA register + TA′ register < 0
MODULO 64 arithmetic is used to ensure that a positive value is loaded
into TX(A) counter, i.e., TA register + TA′ register + 40 hex is loaded into
TX(A) counter.
RA register + RA′ register = 0 or 1
RA register – RA′ register = 0 or 1
Reprogram RX(A) counter with RA register value
RA register + RA′ register = 0 or 1
MODULO 64 arithmetic is used to ensure that a positive value is loaded
into RX(A) counter, i.e., RA register + RA′ register + 40 hex is loaded
into RX(A) counter.
TA register = 0 or 1
RA register = 0 or 1
AIC is shut down. Reprogram TA or RA registers after a reset.
TA register < 4 in word mode
TA register < 5 in byte mode
RA register < 4 in word mode
RA register < 5 in byte mode
The AIC serial port no longer operates. Reprogram TA or RA registers
after a reset.
TB register < 15
ADC no longer operates
RB register < 15
DAC no longer operates
AIC and DSP cannot communicate
Hold last DAC output
2.20 Operation With Conversion Times Too Close Together
If the difference between two successive D/A conversion frame syncs is less than 1/25 kHz, the AIC
operates improperly. In this situation, the second D/A conversion frame sync occurs too quickly, and there
is not enough time for the ongoing conversion to be completed. This situation can occur if the A and B
registers are improperly programmed or if the A + A′ register result is too small. When incrementally
adjusting the conversion period via the A + A′ register options, the designer should not violate this
requirement. See Figure 2–4.
t1
t2
Frame Sync
(FSX or FSR)
Ongoing Conversion
t2 – t1 ≤ 1/25 kHz
Figure 2–4. Conversion Times Too Close Together
2.21 More Than One Receive Frame Sync Occurring Between Two Transmit
Frame Syncs – Asynchronous Operation
When incrementally adjusting the conversion period via the A + A′ or A – A′ register options, a specific
protocol is followed. The command to use the incremental conversion period adjust option is sent to the AIC
during an FSX frame sync. The ongoing conversion period is then adjusted; however, either receive
conversion period A or conversion period B may be adjusted. For both transmit and receive conversion
periods, the incremental conversion period adjustment is performed near the end of the conversion period.
If there is sufficient time between t₁ and t₂, the receive conversion period adjustment is performed during
receive conversion period A. Otherwise, the adjustment is performed during receive conversion period B.
The adjustment command only adjusts one transmit conversion period and one receive conversion period.
To adjust another pair of transmit and receive conversion periods, another command must be issued during
a subsequent FSX frame (see Figure 2–5).
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