TLC32047C Datasheet, PDF (16/61 Pages) Texas Instruments – Wide-Band Analog Interface Circuit

1.5 Terminal Functions (continued)
TERMINAL
I/O
NAME
NO.
DESCRIPTION
D11OUT
3 O In the dual-word (telephone interface) mode, bit D11 of the control register is output to
D11OUT. When the device is reset, bit D11 is initialized to 0 (see DX Serial Data Word
Format). The output update is immediate upon changing bit D11.
EODR
End of data receive. During the word-mode timing, a low-going pulse occurs on EODR
immediately after the 16 bits of A/D information have been transmitted from the AIC to
the TMS320 serial port. EODR can be used to interrupt a microprocessor upon
completion of serial communications. Also, EODR can be used to strobe and enable
external serial-to-parallel shift registers, latches, or external FIFO RAM, and to facilitate
parallel data bus communications between the DSP and the serial-to-parallel shift
registers. During the byte-mode timing, EODR goes low after the first byte has been
transmitted from the AIC to the TMS320 serial port and is kept low until the second byte
has been transmitted. The TMS320C17 can use this low-going signal to differentiate
between first and second bytes.
DGTL GND
9
Digital ground for all internal logic circuits. Not internally connected to ANLG GND.
FSD
1 O Frame sync data. The FSD output remains high during primary communication. In the
dual-word (telephone interface) mode, the FSD output is identical to the FSX output
during secondary communication.
WORD-BYTE
I WORD-BYTE allows differentiation between the word and byte data format (see
DATA-DR/CONTROL and Table 2-1 for details).
FSR
4 O Frame sync receive. FSR is held low during bit transmission. When FSR goes low, the
TMS320 serial port begins receiving bits from the AIC via DR of the AIC. The most
significant DR bit is present on DR before FSR goes low (see Serial Port Sections and
Internal Timing Configuration Diagrams).
FSX
14 O Frame sync transmit. When FSX goes low, the TMS320 serial port begins transmitting
bits to the AIC via DX of the AIC. FSX is held low during bit transmission (see Serial Port
Sections and Internal Timing Configuration Diagrams).
IN+
26 I Noninverting input to analog input amplifier stage
IN –
25 I Inverting input to analog input amplifier stage
MSTR CLK
6
I Master clock. MSTR CLK is used to derive all the key logic signals of the AIC, such as
the shift clock, the switched-capacitor filter clocks, and the A/D and D/A timing signals.
The internal timing configuration diagram shows how these key signals are derived. The
frequencies of these signals are synchronous submultiples of the master clock
frequency to eliminate unwanted aliasing when the sampled analog signals are
transferred between the switched-capacitor filters and the ADC and DAC converters
(see the Internal Timing Configuration).
OUT+
22 O Noninverting output of analog output power amplifier. OUT+ drives transformer hybrids
or high-impedance loads directly in a differential or a single-ended configuration.
OUT–
21 O Inverting output of analog output power amplifier. OUT– is functionally identical with and
complementary to OUT+.
REF
8 I/O Internal voltage reference is brought out on REF. An external voltage reference can be
applied to REF to override the internal voltage reference.
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