OMAP4470_15 Datasheet, PDF (439/450 Pages) Texas Instruments – Multimedia Device Engineering Sample ES1.0

Public Version
OMAP4470
www.ti.com
SWPS048A – AUGUST 2012 – REVISED JANUARY 2013
A.4.3.1.3 Step 3: Frequency-domain Specification Guidelines
With the information in Step 1 and Step 2, the PCB designers can draw the PCB differential lines
satisfying the Step 1 and Step 2 requirements.
However, although the PCB designers draw the lines carefully, the lines can have poor electrical
performance due to many reasons.
The vertical connections such as vias and nonuniform line connection can degrade the electrical
performance of the differential lines. And the ground design around the lines can also affect the electrical
performance.
So, to ensure that the differential lines are well designed, the frequency-domain behavior must be
compared to the frequency-domain specification in Section A.4.2.4, Step 3: Frequency-domain
Specification Guidelines for OMAP Boards.
1. Intralane frequency-domain specification
– Differential-mode characteristics: Sdd12, Sdd11 / Sdd22
– Common-mode characteristics: Scc11/Scc22
– Mode-conversion characteristics: Scd11, Scd12, Scd21, Scd22, Sdc11, Sdc12, Sdc21, Sdc22
2. Interlane frequency-domain specification
– Differential-mode characteristics: Sdd11 / Sdd22
– Common-mode characteristics: Scc11 / Scc22
A.4.3.2 DSI1_1 and DSI1_2 MIPI DSI1 @ 900 Mbps (Up to 3 Data Lanes), @ 824 Mbps (Up to 4 Data
Lanes) Device PCB Guideline
NOTE
The DSI1_1 and DSI1_2 MIPI DSI1 application timings are described in Section 5.5.2.3,
Display Serial Interface (DSI) (especially, the timing conditions specified in the “Timing
Conditions” tables of this section).
NOTE
If the skew degradation due to the total interconnect (from the transmitter ball to the receiver
ball) between the clock and the data lanes is less than ±192 ps (instead of ±222 ps in the
MIPI D-PHY specification) then 900 Mbps (450 MHz) per data lane is achievable with 4 data
lanes at OPP100 and OPP50 operating points.
In this section, the PCB guidelines for DSI1 working up to 900 Mbps are presented based on the three-
step design and validation methodology described on Section A.4.2, Three-step Design and Validation
Methodology for OMAP Boards.
A.4.3.2.1 Step 1: General Guidelines
The general guidelines for the PCB differential lines of DSI1 are given as:
• Single-ended Z₀ = 50 Ω
• Total conductor length on OMAP board < 100 mm.
In the step, the general rule of thumb for the space S = 2 * W is not designated (see Figure A-24). It is
because although the S = 2 * W rule is a good rule of thumb, it is not always the best solution. The
electrical performance will be checked with the frequency-domain specification in Step 3. Even though the
designers does not follow the S = 2 * W rule, the differential lines are ok if the lines satisfy the frequency-
domain specification in Step 3.
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OMAP4470 Processor Multimedia Device PCB Guideline 439
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