OMAP4470_15 Datasheet, PDF (245/450 Pages) Texas Instruments – Multimedia Device Engineering Sample ES1.0

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(6) CA3 = Bank M
Public Version
OMAP4470
SWPS048A – AUGUST 2012 – REVISED JANUARY 2013
Read Begins
DD500
DD509
DD507
DD512
DD508
DD514
DD514
lpddr2_ck
lpddr2_nck
lpddr2_caZ CA1 CA2
CA3 CA4 CA5 CA6
CA7
[Cmd] Activate Nop Activate Read
Nop Precharge
Nop REFab Nop
REFab
Nop
ANY
SWPS040-032
Figure 5-39. EMIF—DDR Mode—SDRAM Core Parameters—Active to Read, Precharge, Active to
Precharge, Write, Write to Read, Active Bank A to Active Bank B Commands^{(1)(2)(3)(4)(5)(6)(7)(8)(9)(10)}
(1) X = [3:0]
(2) Y = [31:0]
(3) Z = [9:0]
(4) CA1 = Bank A Row Address
(5) CA2 = Row Address
(6) CA3 = Bank B Row Address
(7) CA4 = Row Address
(8) CA5 = Bank A Column Address
(9) CA6 = Column Address
(10) CA7 = Bank A
Completion of Burst Write
lpddr2_ck
lpddr2_nck
lpddr2_caZ
[Cmd]
lpddr2_dqsX
lpddr2_ndqsX
lpddr2_dY
CA1 CA2
Write
CA3
Nop
Nop
Nop
Nop
Precharge
DD405_MAX
DD510
DOUT A0 DOUT A1 DOUT A2
DOUT A3
Nop
SWPS040-033
Figure 5-40. EMIF—DDR Mode—SDRAM Core Parameters—Write Recovery Time^{(1)(2)(3)(4)(5)(6)}
(1) X = [3:0]
(2) Y = [31:0]
(3) Z = [9:0]
(4) CA1 = Bank A Column Address A
(5) CA2 = Column Address
(6) CA3 = Bank A
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Timing Requirements and Switching Characteristics 245
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