OMAP4470_15 Datasheet, PDF (309/450 Pages) Texas Instruments – Multimedia Device Engineering Sample ES1.0

Public Version
OMAP4470
www.ti.com
SWPS048A – AUGUST 2012 – REVISED JANUARY 2013
(3) To have an idea of the output OMAP4 ball load supported for this application, you can consider the following:
Output OMAP4 ball load = Far End load + 1.34 pF/cm (typical) x trace length (cm).
Table 5-98. McSPI3 Timing Requirements—Master Mode⁽²⁾
NO.
PARAMETER
OPP100, OPP119
OPP50
UNIT
MIN
MAX
MIN
MAX
SM4
t_{su(SOMI-CLKAE)} Setup time, mcspi3_somi valid before
2.29
2.29
ns
mcspi3_clk⁽¹⁾ active edge
SM5
t_{h(clkAE-SOMI)}
Hold time, mcspi3_somi valid after
2.67
2.67
ns
mcspi3_clk⁽¹⁾ active edge
(1) This timing applies to all configurations regardless of mcspi_clk polarity and which clock edges are used to drive output data and
capture input data.
(2) See DM Operating Condition Addendum for CORE OPP voltages.
Table 5-99. McSPI3 Switching Requirements—Master Mode⁽⁸⁾
NO.
PARAMETER
OPP100, OPP119
OPP50
UNIT
SM1
SM2
SM3
SM6
1 / t_c(clk)
t_w(clkL)
t_w(clkH)
t_dc(clk)
t_j(clk)
t_R(clk)
t_F(clk)
t_d(clk-SIMO)
Frequency⁽¹⁾, mcspi3_clk⁽⁴⁾
Typical pulse duration, mcspi3_clk⁽⁴⁾ low
Typical pulse duration, mcspi3_clk⁽⁴⁾ high
Duty cycle error, mcspi3_clk
Jitter standard deviation⁽³⁾, mcspi3_clk
Rise time, mcspi3_clk
Fall time, mcspi3_clk
Delay time, mcspi3_clk⁽⁴⁾ active edge to
mcspi3_simo transition
MIN
MAX
48⁽⁷⁾
0.5*P⁽²⁾
0.5*P⁽²⁾
–1042
1042
65
3820.4
3442.4
–3.57
3.57
MIN
MAX
48⁽⁷⁾
0.5*P⁽²⁾
0.5*P⁽²⁾
–1042
1042
65
3820.4
3442.4
–3.57
3.57
MHz
ns
ns
ps
ps
ps
ps
ns
SM7
t_d(CS-SIMO) Delay time, mcspi3_cs0 active edge to
mcspi3_simo transition
3.57
3.57
ns
SM8
t_d(CS-clk)
Delay time, mcspi3_cs0 active to
PHA = 1⁽¹⁾ A⁽⁵⁾ – 4.2
A⁽⁵⁾ – 4.2
ns
mcspi3_clk⁽⁴⁾ first edge
PHA = 0⁽¹⁾ B⁽⁶⁾ – 4.2
B⁽⁶⁾ – 4.2
ns
SM9
t_d(clk-CS)
Delay time, mcspi3_clk⁽⁴⁾ last edge PHA = 1⁽¹⁾ B⁽⁶⁾ – 4.2
B⁽⁶⁾ – 4.2
ns
to mcspi3_cs0 inactive
PHA = 0⁽¹⁾ A⁽⁵⁾ – 4.2
A⁽⁵⁾ – 4.2
ns
t_R(SIMO)
t_F(SIMO)
t_R(CS)
t_F(CS)
Rise time, mcspi3_simo
Fall time, mcspi3_simo
Rise time, mcspi3_cs0
Fall time, mcspi3_cs0
3820.4
3442.4
3820.4
3442.4
3820.4
ps
3442.4
ps
3820.4
ps
3442.4
ps
(1) The polarity of mcspi3_clk and the active edge (rising or falling) on which mcspi3_simo is driven and mcspi3_somi is latched is all
software configurable:
– mcspi3_clk phase programmable with the bit PHA of MCSPI_Ch(i)CONF register: PHA = 1 (Modes 1 and 3).
– mcspi3_clk phase programmable with the bit PHA of MCSPI_Ch(i)CONF register: PHA = 0 (Modes 0 and 2).
For more information, see the McSPI environment chapter, Data Format Configurations section of the OMAP4470 TRM for modes and
phase correspondence descriptions.
(2) P = mcspi3_clk clock period
(3) The jitter probability density can be approximated by a Gaussian function.
(4) This timing applies to all configurations regardless of mcspi3_clk polarity and which clock edges are used to drive output data and
capture input data.
(5) Case P = 48 MHz: A = (TCS + 1) * T_SPICLKREF (TCS is a bit field of MCSPI_Ch(i)CONF register)
Case P < 48 MHz: A = (TCS + 0.5) * F_RATIO * T_SPICLKREF (TCS is a bit field of MCSPI_Ch(i)CONF register)
For more information, see the McSPI chapter of the OMAP4470 TRM.
(6) B = (TCS + 0.5) * T_SPICLKREF * F_RATIO (TCS is a bit field of MCSPI_Ch(i)CONF register, F_RATIO: Even ≥ 2).
For more information, see the McSPI chapter of the OMAP4470 TRM.
(7) This McSPI3 output clock frequency is based on an output PER DPLL configured at 96 MHz.
For more information regarding the registers configuration, see Power, Reset and Clock Management / Clock Management Functional
Description / Internal Clock Sources/Generators / DPLL_PER Description section of the OMAP4470 TRM.
Copyright © 2012–2013, Texas Instruments Incorporated
Timing Requirements and Switching Characteristics 309
Submit Documentation Feedback
Product Folder Links: OMAP4470