OMAP4470_15 Datasheet, PDF (188/450 Pages) Texas Instruments – Multimedia Device Engineering Sample ES1.0

OMAP4470
Public Version
SWPS048A – AUGUST 2012 – REVISED JANUARY 2013
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Table 4-12. fref_clkx_out Output Clock Switching Characteristics^(1)(6)(7)(9) (continued)
NAME
LB0 = 0
t_R(clkOUT1)
t_F(clkOUT1)
t_R(clkOUT1)
t_F(clkOUT1)
DESCRIPTION
Rise time, fref_clkx_out
Fall time, fref_clkx_out
Rise time, fref_clkx_out
Fall time, fref_clkx_out
MIN
2.2⁽³⁾⁽⁵⁾
2.2⁽³⁾⁽⁵⁾
TYP
0.7⁽³⁾⁽⁵⁾
0.7⁽³⁾⁽⁵⁾
MAX
14.3⁽⁴⁾
14.3⁽⁴⁾
10.4⁽⁴⁾
10.4⁽⁴⁾
UNIT
ns
ns
ns
ns
(1) In fref_clkx_out, x = 0, 1, 2, 3, 4, or 5
(2) A divide factor from 1 to 16 can be applied on this clock frequency.
For more information, see the SCRM.AUXCLK[0:5] register, CLKDIV bitfield in the OMAP4470 TRM.
(3) At minimum load
(4) At maximum load (maximum frequency: 104 MHz)
(5) Caution: this creates EMI parasitics up to 1.2 ns.
(6) In this table the rise and fall times are calculated for 10% to 90% of VDDS.
For more information on the corresponding OMAP4 VDDS power supply name, see Table 2-1, POWER [9] column with the ball name.
(7) clkx_out is the external clock signal at the fref_clkx_out output pin.
dpll_out is the internal clock signal at the dpll output, before the clock divider controlled by CLKDIV.
(8) ±50 ppm is the clock frequency stability/accuracy and ±5 ppm takes into account the aging effects.
(9) t_{J(fref_xtal_in)} or t_{J(fref_slicer_in)} corresponds to the external jitter coming to the fref_xtal_in or fref_slicer_in input PAD.
fref_clkx_out
FREF0
FREF1
Figure 4-6. fref_clkx_out Output Clocks⁽¹⁾
(1) In fref_clkx_out, x = 0, 1, 2, 3, 4, or 5
4.3 DPLLs, DLLs Specifications
FREF1
SWPS039-009
For more information, see:
NOTE
• Power, Reset and Clock Management / Clock Management Functional / Internal Clock
Sources/Generators / Generic DPLL Overview section
and
• Display Subsystem / Display Subsystem Overview section of the OMAP4470 ES2.x
TRM.
The applicative subsystem integrates nine DPLLs and four DLLs. The PRM and CM drive six of them,
while the display subsystem controls three other DPLLs (DSI1_1 DPLL, DSI1_2 DPLL, and HDMI DPLL).
The six main DPLLs are:
• DPLL1 (MPU)
• DPLL2 (IVA)
• DPLL3 (CORE)
• DPLL4 (PER)
• DPLL5 (ABE)
• DPLL6 (USB)
NOTE
Of the nine DPLLs embedded in the OMAP4470 device, the DSI1_1 DPLL, DSI1_2 DPLL,
and HDMI DPLL are controlled directly by the display subsystem.
188 Clock Specifications
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