OMAP4470_15 Datasheet, PDF (288/450 Pages) Texas Instruments – Multimedia Device Engineering Sample ES1.0

OMAP4470
Public Version
SWPS048A – AUGUST 2012 – REVISED JANUARY 2013
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Table 5-65. McBSP3 Timing Requirements—I2S/PCM—Slave Mode^(4)(5)(8) (continued)
NO.
PARAMETER
OPP100, OPP119
OPP50
UNIT
MIN
MAX
MIN
MAX
For balls: AG25 / AF25 / AE25 / AF26 (abe_mcbsp3_dr / abe_mcbsp3_dx / abe_mcbsp3_clkx / abe_mcbsp3_fsx)—Multiplexing
mode 1
BS0
BS1
BS2
BS3
1 / t_c(clk)
t_w(clkL)
t_w(clkH)
t_dc(clk)
t_j(clk)
t_{su(fsV-clkAE)}
Frequency⁽¹⁾, abe_mcbsp3_clk⁽⁶⁾
Typical pulse duration, abe_mcbsp3_clk⁽⁶⁾ low
Typical pulse duration, abe_mcbsp3_clk⁽⁶⁾ high
Duty cycle error, abe_mcbsp3_clk⁽⁶⁾
Cycle jitter⁽³⁾, abe_mcbsp3_clk⁽⁶⁾
Setup time, abe_mcbsp3_fs⁽⁷⁾ valid before
abe_mcbsp3_clk⁽⁶⁾ active edge
12.288
0.5*P⁽²⁾
0.5*P⁽²⁾
–2035 2035
1221
14.3
6.144
0.5*P⁽²⁾
0.5*P⁽²⁾
–4069 4069
2000
30.4
MHz
ns
ns
ps
ps
ns
BS4
t_h(clkAE-fsV)
Hold time, abe_mcbsp3_fs⁽⁷⁾ valid after
14.3
30.4
ns
abe_mcbsp3_clk⁽⁶⁾ active edge
BS6
t_{su(drV-clkAE)}
Setup time, abe_mcbsp3_dr valid before
14.3
30.4
ns
abe_mcbsp3_clk⁽⁶⁾ active edge
BS7
t_h(clkAE-drV)
Hold time, abe_mcbsp3_dr valid after
abe_mcbsp3_clk⁽⁶⁾ active edge
14.3
30.4
ns
(1) Related to the input maximum frequency supported by the McBSP module.
(2) P = abe_mcbsp3_clkx / abe_mcbsp3_clkr period in ns
(3) Maximum cycle jitter supported by abe_mcbsp3_clkx / abe_mcbsp3_clkr input clock.
(4) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified.
(5) The timings apply to all configurations regardless of abe_mcbsp3_clk polarity and which clock edges are used to drive output data and
capture input data.
(6) abe_mcbsp3_clk corresponds to either abe_mcbsp3_clkx or abe_mcbsp3_clkr; abe_mcbsp3_clkr is available in 6-pin mode only.
(7) abe_mcbsp3_fs corresponds to either abe_mcbsp3_fsx or abe_mcbsp3_fsr; abe_mcbsp3_fsr is available in 6-pin mode only.
(8) See DM Operating Condition Addendum for CORE OPP voltages.
Table 5-66. McBSP3 Switching Characteristics—I2S/PCM—Slave Mode⁽¹⁾⁽²⁾
NO.
PARAMETER
OPP100, OPP119
OPP50
UNIT
MIN
MAX
MIN
MAX
For balls: AE16 / AF16 / AG16 (abe_mcbsp3_dx / abe_mcbsp3_clkx / abe_mcbsp3_fsx)—Multiplexing mode 2
BS5
t_{d(clkxAE-dxV)}
Delay time, input abe_mcbsp3_clkx active
–16.4
22.3
–34.1
38.1
ns
edge to output abe_mcbsp3_dx valid
t_R(dx)
Rise time, output abe_mcbsp3_dx
400
6500
400
6500
ps
t_F(dx)
Fall time, output abe_mcbsp3_dx
400
6500
400
6500
ps
For balls: AF25 / AE25 / AF26 (abe_mcbsp3_dx / abe_mcbsp3_clkx / abe_mcbsp3_fsx)—Multiplexing mode 1
BS5
t_{d(clkxAE-dxV)}
Delay time, input abe_mcbsp3_clkx active
–16.4
20.3
–34.0
36.1
ns
edge to output abe_mcbsp3_dx valid
t_R(dx)
t_F(dx)
Rise time, output abe_mcbsp3_dx
Fall time, output abe_mcbsp3_dx
400
6500
400
6500
ps
400
6500
400
6500
ps
(1) The timings apply to all configurations regardless of abe_mcbsp3_clk polarity and which clock edges are used to drive output data and
capture input data.
(2) See DM Operating Condition Addendum for CORE OPP voltages.
288 Timing Requirements and Switching Characteristics
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