OMAP4470_15 Datasheet, PDF (377/450 Pages) Texas Instruments – Multimedia Device Engineering Sample ES1.0

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OMAP4470
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SWPS048A – AUGUST 2012 – REVISED JANUARY 2013
sdmmc1_clk
sdmmc1_cmd
sdmmc1_dat[n:0]
HSSDR501
HSSDR502
HSSDR503
HSSDR507
HSSDR502
HSSDR504
HSSDR508
Figure 5-121. MMC/SD/SDIO 1 Interface—High-Speed SDR50—Receiver Mode⁽¹⁾
SWPS040-078
(1) In sdmmc1_dat[n:0], n up to 7
5.7.1.1.4 MMC/SD/SDIO 1 Interface—High-Speed SD Mode—DDR50
Table 5-199 and Table 5-200 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 5-122 through Figure 5-123).
Table 5-198. MMC/SD/SDIO 1 Interface Timing Conditions—High-Speed SD Mode—DDR50^(1)(2)(3)(4)
TIMING CONDITION PARAMETER
VALUE
UNIT
MIN
MAX
Input Conditions
t_R
Input signal rise time
t_F
Input signal fall time
PCB Conditions
700
2750
ps
700
2750
ps
Number of external peripherals
1
Far end load
10
pF
Trace length
10
cm
Characteristic impedance
SanDisk Extreme III cards
45
55
Ω
Other card types
20
70
(1) IO settings: SPEEDCTRL = 1
For more information, see
– The Control Module Functional Description / Extended-Drain I/O and PBIAS Cell / Extended-Drain I/O section or
– The Control Module / Control Module Functional Description / Functional Register Description / Signal Integrity Parameter Control
Registers with Pad Group Assignment / Device Interfaces Signal Group Controls Mapping section
of the OMAP4470 TRM.
(2) In this table the rise and fall times are calculated for the V_IL / V_IH described in Section 3.3.11, MMC/SDIO DC Electrical Characteristics.
(3) For more information on SDMMC ESD guideline examples, see Section A.3.2.2.1, ESD Implementation—MMC/SD/SDIO 1
Interface—SD Mode.
(4) To have an idea of the output OMAP4 ball load supported for this application, you can consider the following:
Output OMAP4 ball load = Far End load + 1.34 pF/cm (typical) x trace length (cm).
Table 5-199. MMC/SD/SDIO 1 Interface Timing Requirements—High-Speed SD Mode—DDR50⁽¹⁾⁽²⁾
NO.
PARAMETER
MMC/SD/SDIO 1 Interface (1.8-V IO)
HSSD3
t_{su(cmdV-clkH)}
Setup time, sdmmc1_cmd valid before
sdmmc1_clk rising clock edge
HSSD4
t_h(clkH-cmdV)
Hold time, sdmmc1_cmd valid after
sdmmc1_clk rising clock edge
HSSD7
t_su(dV-clkH)
Setup time, sdmmc1_dat[n:0] valid before
sdmmc1_clk rising clock edge
HSSD8
t_h(clkH-dV)
Hold time, sdmmc1_dat[n:0] valid after
sdmmc1_clk rising clock edge
OPP100, OPP119
MIN
MAX
5
2
0.9
2
OPP50
MIN
MAX
25.3
1.1
10.2
1.1
UNIT
ns
ns
ns
ns
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Timing Requirements and Switching Characteristics 377
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