OMAP4470_15 Datasheet, PDF (258/450 Pages) Texas Instruments – Multimedia Device Engineering Sample ES1.0

OMAP4470
Public Version
SWPS048A – AUGUST 2012 – REVISED JANUARY 2013
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Table 5-34. CPI Timing Requirements—Video and Graphics Digitizer 1.8-V Mode⁽⁴⁾⁽⁶⁾ (continued)
NO.
PARAMETER
OPP100, OPP119
UNIT
MIN
MAX
ISP12
t_{su(fldV-pclkH)}
Setup time, input field identification cam2_fld valid before input pixel 0.75
ns
clock cam2_pclk rising / falling edge
ISP13
t_{h(pclkH-fldV)}
Hold time, input field identification cam2_fld valid after input pixel
0.96
ns
clock cam2_pclk rising / falling edge
(1) Related with the input maximum frequency supported by the ISP module in 8-bit mode with 8 to 16 data bits conversion bridge enabled.
(2) P = cam2_pclk period in ns
(3) Maximum cycle jitter supported by cam2_pclk input clock.
(4) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified.
(5) n = 15 (Data bus size is limited to 8 bits. So the bits configuration is either cam2_d[7:0] or cam2_d[8:15]). Lines not connected must be
tied low. When the number of data lines is less than cam2_d[n:0], data lines can be connected to the upper or lower lines of
cam2_d[n:0]. Lines not connected must be tied low.
For more information about video port mapping, see the OMAP4470 TRM.
(6) See DM Operating Condition Addendum for OPP voltages.
cam2_pclk
ISP1
ISP3
ISP2
cam2_vs
ISP4
ISP5
cam2_hs
ISP6
ISP7
ISP8
ISP9
cam2_d[N:0]
D(0)
D(n-2)
D(n-1)
D(0)
D(n-2)
D(n-1)
cam2_wen
ISP10
ISP11
cam2_fld
Figure 5-54. CPI—Video and Graphics Digitizer—1.8-V Progressive Mode⁽¹⁾⁽²⁾
SWPS038-048
(1) The polarity of cam2_pclk, cam2_fld, cam2_vs, and cam2_hs are software configurable. Optionally, the cam2_wen signal can be used
as an external memory write-enable signal. For further details, see the OMAP4470 TRM.
(2) N = 15 (Data bus size is limited to 8 bits. So the bits configuration is either cam2_d[7:0] or cam2_d[8:15]). Lines not connected must be
tied low. When the number of data lines is less than cam2_d[N:0], data lines can be connected to the upper or lower lines of
cam2_d[N:0]. Lines not connected must be tied low.
For more information about video port mapping, see the OMAP4470 TRM.
258 Timing Requirements and Switching Characteristics
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