OMAP4470_15 Datasheet, PDF (131/450 Pages) Texas Instruments – Multimedia Device Engineering Sample ES1.0

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OMAP4470
www.ti.com
SWPS048A – AUGUST 2012 – REVISED JANUARY 2013
3.3.2 LPDDR2 DC Electrical Characteristics
Table 3-5 summarizes the LPDDR2 dc electrical characteristics in multiplexing mode 0.
NOTE
For more information on the IO cell configurations (i[2:0], sr[1:0], vref_tap[1:0]), see the
Control Module / Control Module Functional Description / Functional Register Description /
Signal Integrity Parameter Control Registers With Pad Group Assignment section of the
OMAP4470 TRM.
Table 3-5. LPDDR2 DC Electrical Characteristics
PARAMETER
MIN
NOM
MAX
UNIT
Signals in Mode 0: lpddr21_dq[31:0], lpddr21_ca[9:0], lpddr21_dm[3:0], lpddr21_ncs[1:0], lpddr21_cke[1:0], lpddr22_dq[31:0],
lpddr22_ca[9:0], lpddr22_dm[9:0], lpddr22_ncs[1:0], lpddr22_cke[1:0]
(Top Balls: E29 / D28 / B27 / A27 / A26 / B26 / A25 / A24 / B19 / A19 / A18 / A17 / B17 / A13 / A12 / B12 / N28 / N29 / M29 / L28 / K28 /
K29 / J29 / H29 / B8 / A8 / A7 / B6 / B5 / A5 / A4 / B3 / AJ27 / AH27 / AH26 / AH25 / AJ25 / AJ20 / AH20 / AH19 / AJ18 / AH17 / B22 / A21
/ F28 / B11 / AH24 / AJ24 / AH23 / AJ23 / L2 / M1 / N1 / U2 / V1 / W2 / W1 / Y2 / AE1 / AF1 / AG1 / AG2 / AJ3 / AH4 / AJ5 / AH6 / C2 / D1
/ E1 / E2 / F2 / G1 / H1 / H2 / AJ9 / AJ10 / AH10 / AH11 / AJ12 / AJ13 / AH13 / AJ14 / R29 / T29 / U29 / V29 / W28 / AC29 / AD29 / AD28 /
AE28 / AF29 / AB1 / AC2 / L1 / AH7 / Y28 / W29 / AA29 / Y29)
V_IH
Input high-level threshold
0.5 * vddx_lpddr2⁽⁷⁾ +
0.13
vddx_lpddr2⁽⁷⁾ + 0.2
V
V_IL
Input low-level threshold
–0.2
0.5 * vddx_lpddr2⁽⁷⁾ –
V
0.13
V_HYS(1) Input hysteresis voltage
NA⁽¹⁾
mV
C_IN
Input capacitance
V_OH
Output high-level threshold (I_OH = 0.1 mA)
V_OL
Output low-level threshold (I_OL = 0.1 mA)
0.9 * vddx_lpddr2⁽⁷⁾
3
pF
V
0.1 * vddx_lpddr2⁽⁷⁾
V
Z_O
Output impedance
i[2:0] = 000 (Drv5)
1.66 * R_REF
Ω
i[2:0] = 001 (Drv6)
1.33 * R_REF
i[2:0] = 010 (Drv7)
i[2:0] = 011 (Drv8)
1.14 * R_REF
R_REF(2)
i[2:0] = 100 (Drv9)
0.88 * R_REF
i[2:0] = 101 (Drv10)
0.8 * R_REF
i[2:0] = 110 (Drv11)
0.73 * R_REF
i[2:0] = 111 (Drv12)
0.67 * R_REF
t_OT
Output transition time/turn- sr[1:0] = 00 (Fastest)
250
ps
on time (rise time, t_R or fall
time, t_F) measured between
sr[1:0] = 01 (Faster)
315
10% to 90% of PAD
sr[1:0] = 10 (Fast)
340
voltage^(3)(4)(6)
sr[1:0] = 11 (Slow)
390
Maximum noise on the IO
supply voltage^(3)(5)(6)
sr[1:0] = 00 (Fastest)
sr[1:0] = 01 (Faster)
215
mV_PP
110
sr[1:0] = 10 (Fast)
108
sr[1:0] = 11 (Slow)
110
Signals in Mode 0: lpddr21_dqs[3:0], lpddr21_ndqs[3:0], lpddr21_ck, lpddr21_nck, lpddr22_dqs[3:0], lpddr22_ndqs[3:0], lpddr22_ck,
lpddr22_nck
(Top Balls: A23 / B23 / A20 / B20 / G28 / G29 / B10 / A10 / AJ21 / AH21 / AA1 / AA2 / AD2 / AD1 / K2 / K1 / AH8 / AJ8 / AB28 / AB29)
V_SWING Input differential swing
(DC)
0.26
vddx_lpddr2⁽⁷⁾ + 0.4
V
V_CM
Input common mode range
V_HYS(1) Input hysteresis voltage
0.4 * vddx_lpddr2⁽⁷⁾
NA⁽¹⁾
0.6 * vddx_lpddr2⁽⁷⁾
V
mV
C_IN
Input capacitance
V_OH
Output high-level threshold (I_OH = 0.1 mA)
V_OL
Output low-level threshold (I_OL = 0.1 mA)
0.9 * vddx_lpddr2⁽⁷⁾
3
pF
V
0.1 * vddx_lpddr2⁽⁷⁾
V
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Electrical Characteristics 131