THS7327 Datasheet, PDF (21/26 Pages) Texas Instruments – 3-Channel RGBHV Video Buffer with I2C Control, Selectable Filters, Monitor Pass-Thru,2:1 Input MUX, and Selectable Input Bias Modes

www.ti.com
THS7327
SLOS502 – SEPTEMBER 2006
Table 4. THS7327 Channel Register (HV Sync Channel + ADC State) Bit Decoder Table – Use in
Conjunction With Register Bit Code (0000 0100)
BIT
FUNCTION
(MSB)
7
6
Reserved – Do Not Care
Monitor Pass-Thru Path Disable Mode
(Use in Conjunction with Table 3)
5
Buffer Path Disable Mode (Use in
Conjunction with Table 3)
4, 3 Vertical Sync Channel MUX Selection
2, 1
0
(LSB)
Horizontal Sync Channel MUX
Selection
HV Sync Paths Disable Mode
BIT
VALUE(S)
X
0
1
0
1
00
01
10
11
00
01
10
11
0
1
RESULT
Reserved – Do Not Care
Disable Monitor Channel if Ch. 1-3 bits 2,1,0 = 000
Enable Monitor Channel 1-3 bits 2,1,0 = 000
Disable Buffer Channel if Channel 1-3 bits 2,1,0 = 000
Enable Buffer Channel if Channel 1-3 bits 2,1,0 = 000
MUX Input A
MUX Input B
Reserved – Do Not Care
Reserved – Do Not Care
MUX Input A
MUX Input B
Reserved – Do Not Care
Reserved – Do Not Care
Disable H and V Sync Channels (all channels)
Enable H and V Sync Channels (all channels)
Bit (MSB) 7 – Reserved – Do Not Care
Bit 6 – Enables or Disables the Respective Monitor Channel if Registers Ch. 1 (0000 0001), Ch. 2 (0000 0010),
and/or Ch.3 (0000 0011) are set to the Disable State (XXXX X000).
Bit 5 – Enables or Disables the Respective Buffer Channel if Registers Ch. 1 (0000 0001), Ch. 2 (0000 0010),
and/or Ch.3 (0000 0011) are set to the Disable State (XXXX X000).
Bits 4, 3 – Selects the Input MUX channel for the Vertical Sync
Bits 2, 1 – Selects the Input MUX channel for the Horizontal Sync
Bit 0 (LSB) – Configures the Buffer path Enable/Disable state when used in conjunction with Table 3.
Submit Documentation Feedback
21