THS7327 Datasheet, PDF (20/26 Pages) Texas Instruments – 3-Channel RGBHV Video Buffer with I2C Control, Selectable Filters, Monitor Pass-Thru,2:1 Input MUX, and Selectable Input Bias Modes

THS7327
SLOS502 – SEPTEMBER 2006
www.ti.com
Channel Register Bit Descriptions
Each bit of the subaddress (channel selection) control register as described above allows the user to individually
control the functionality of the THS7327. The benefit of this process allows the user to control the functionality of
each channel independent of the other channels. The bit description is decoded in Table 3 and Table 4.
Table 3. THS7327 Channel Register (Ch. 1 thru 3) Bit Decoder Table – Use with Register Bit Codes
(0000 0001), (0000 0010), and (0000 0011)
BIT
(MSB)
7
FUNCTION
Sync-Tip Clamp Filter
6, 5, 4, 3
MUX Selection
+
Low Pass Filter
2, 1, 0
(LSB)
Input Mode
+
Operation
BIT
VALUE(S)
0
1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
000
001
010
011
100
101
110
111
RESULT
500-kHz Filter on the STC circuit
5-MHz Filter on the STC circuit
MUX Input A; LPF = 9-MHz
MUX Input A; LPF = 16-MHz
MUX Input A; LPF = 35-MHz
MUX Input A; LPF = 75-MHz
MUX Input A; LPF = Bypass
MUX Input B; LPF = 9-MHz
MUX Input B; LPF = 16-MHz
MUX Input B; LPF = 35-MHz
MUX Input B; LPF = 75-MHz
MUX Input B; LPF = Bypass
Reserved – Do Not Care
Reserved – Do Not Care
Reserved – Do Not Care
Reserved – Do Not Care
Reserved – Do Not Care
Reserved – Do Not Care
Disable Channel if Register 4 bit is 0 - see Table 4
Channel Mute
Input Mode = DC
Input Mode = DC + Shift
Input Mode = AC-Bias
Input Mode = AC-STC with Low Bias
Input Mode = AC-STC with Mid Bias
Input Mode = AC-STC with High Bias
Bits 7 (MSB) – Controls the sync-tip clamp filter. Useful only when AC-STC input mode is selected.
Bit 6, 5, 4, 3 – Selects the Input MUX channel and the Buffer low pass filter
Bits 2, 1, and 0 (LSB) – Configures the channel mode and operation. For the disable code (000), the monitor
path channel is in disabled state. The Buffer path state is disabled if Register 4, bit 0 is set to 0. If Register 4, bit
0 is set to 1, then the Buffer path is enabled while the monitor path is disabled.
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