THS7327 Datasheet, PDF (16/26 Pages) Texas Instruments – 3-Channel RGBHV Video Buffer with I2C Control, Selectable Filters, Monitor Pass-Thru,2:1 Input MUX, and Selectable Input Bias Modes

THS7327
SLOS502 – SEPTEMBER 2006
www.ti.com
APPLICATION INFORMATION (continued)
be placed first in the system. Since the blue color difference channel (P'_B) is next and the red color difference
channel (P'_R) is last, then it also makes logical sense to place the B' signal on the second channel and the R'
signal on the third channel respectfully. Thus hardware compatibility is better achieved when using G'B'R' rather
than R'G'B'. Note that for many G'B'R' systems sync is embeded on all three channels, but may not always be
the case in all systems.
I²C INTERFACE NOTES
The I²C interface is used to access the internal registers of the THS7327. I²C is a two-wire serial interface
developed by Philips Semiconductor (see the I²C-Bus Specification, Version 2.1, January 2000). The bus
consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and
SCL lines are pulled high. All the I²C compatible devices connect to the I²C bus through open drain I/O pins,
SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The
master is responsible for generating the SCL signal and device addresses. The master also generates specific
conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on
the bus under control of the master device. The THS7327 works as a slave and supports the standard mode
transfer (100 kbps) and fast mode transfer (400 kbps) as defined in the I²C-Bus specification. The THS7327 has
been tested to be fully functional with the high-speed mode (3.4 Mbps) but it is not guaranteed at this time.
The basic I²C start and stop access cycles are shown in Figure 9.
The basic access cycle consists of the following:
• A start condition
• A slave address cycle
• Any number of data cycles
• A stop condition
SDA
SCL
S
Start
Condition
Figure 9. I²C Start and Stop Conditions
P
Stop
Condition
GENERAL I²C PROTOCOL
• The master initiates data transfer by generating a start condition. The start condition exist when a
high-to-low transition occurs on the SDA line while SCL is high, as shown in Figure 9. All I²C-compatible
devices should recognize a start condition.
• The master then generates the SCL pulses and transmits the 7-bit address and the read/writedirection bit
R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition
requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 10). All
devices recognize the address sent by the master and compare it to their internal fixed addresses. Only the
slave device with a matching address generates an acknowledge (see Figure 11) by pulling the SDA line low
during the entire high period of the ninth SCL cycle. On detecting this acknowledge, the master knows that a
communication link with a slave has been established.
• The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from
the slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So,
an acknowledge signal can either be generated by the master or by the slave, depending on which one is
the receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as
long as necessary (see Figure 12).
16
Submit Documentation Feedback