THS7327 Datasheet, PDF (18/26 Pages) Texas Instruments – 3-Channel RGBHV Video Buffer with I2C Control, Selectable Filters, Monitor Pass-Thru,2:1 Input MUX, and Selectable Input Bias Modes

THS7327
SLOS502 – SEPTEMBER 2006
www.ti.com
APPLICATION INFORMATION (continued)
During a write cycle, the transmitting device must not drive the SDA signal line during the acknowledge cycle, so
that the receiving device may drive the SDA signal low. After each byte transfer following the address byte, the
receiving device pulls the SDA line low for one SCL clock cycle. A stop condition is initiated by the transmitting
device after the last byte is transferred. An example of a write cycle can be found in Figure 13 and Figure 14.
Note that the THS7327 does not allow multiple write transfers to occur. See Example – Writing to the
THS7327section for more information.
During a read cycle, the slave receiver acknowledges the initial address byte if it decodes the address as its
address. Following this initial acknowledge by the slave, the master device becomes a receiver and
acknowledges data bytes sent by the slave. When the master has received all of the requested data bytes from
the slave, the not acknowledge (A) condition is initiated by the master by keeping the SDA signal high just
before it asserts the stop (P) condition. This sequence terminates a read cycle as shown in Figure 15 and
Figure 16. Note that the THS7327 does not allow multiple read transfers to occur. See Example – Reading
from the THS7327 section for more information.
From Receiver
S Slave Address
W A DATA A DATA A P
From Transmitter
Figure 13. I²C Write Cycle
A = No Acknowledge (SDA High)
A = Acknowledge
S = Start Condition
P = Stop Condition
W = Write
R = Read
Start
Condition
Acknowledge
(From Receiver)
Acknowledge
(Receiver)
Acknowledge
(Transmitter)
SDA
A6 A5
A1 A0 R/W ACK D7 D6
D1 D0 ACK
D7 D6
D1 D0 ACK
I²C Device Address and
Read/Write Bit
First Data
Byte
Other
Last Data Byte
Data Bytes
Figure 14. Multiple Byte Write Transfer
Stop
Condition
S Slave Address R A DATA A DATA A P
Transmitter
Receiver
Figure 15. I²C Read Cycle
A = No Acknowledge (SDA High)
A = Acknowledge
S = Start Condition
P = Stop Condition
W = Write
R = Read
Start
Condition
Acknowledge
(From
Receiver)
Acknowledge
(From
Transmitter)
Not
Acknowledge
(Transmitter)
SDA
A6
A0 R/W ACK D7
D0 ACK
D7 D6
D1 D0 ACK
I²C Device Address and
Read/Write Bit
First Data
Byte
Other
Last Data Byte
Data Bytes
Figure 16. Multiple Byte Read Transfer
Stop
Condition
18
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