THS7327 Datasheet, PDF (19/26 Pages) Texas Instruments – 3-Channel RGBHV Video Buffer with I2C Control, Selectable Filters, Monitor Pass-Thru,2:1 Input MUX, and Selectable Input Bias Modes

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THS7327
SLOS502 – SEPTEMBER 2006
APPLICATION INFORMATION (continued)
Slave Address
Both the SDA and the SCL must be connected to a positive supply voltage via a pullup resistor. These resistors
should comply with the I²C specification that ranges from 2 kΩ to 19 kΩ. When the bus is free, both lines are
high. The address byte is the first byte received following the START condition from the master device. The first
5 Bits (MSBs) of the address are factory preset to 01011. The next two bits of the THS7327 address are
controlled by the logic levels appearing on the I²C-A1 and I²C-A0 pins. The I²C-A1 and I²C-A0 address inputs
can be connected to V_S+ for logic 1, GND for logic 0, or it can be actively driven by TTL/CMOS logic levels. The
device address is set by the state of these pins and is not latched. Thus, a dynamic address control system
could be used to incorporate several devices on the same system. Up to four THS7327 devices can be
connected to the same I²C-Bus without requiring additional glue logic. Table 1 lists the possible addresses for
the THS7327.
Bit 7 (MSB)
0
0
0
0
0
0
0
0
Bit 6
1
1
1
1
1
1
1
1
Table 1. THS7327 Slave Addresses
FIXED ADDRESS
Bit 5
0
0
0
0
0
0
0
0
Bit 4
1
1
1
1
1
1
1
1
Bit 3
1
1
1
1
1
1
1
1
SELECTABLE WITH
ADDRESS PINS
Bit 2 (A1)
Bit 1 (A0)
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
READ/WRITE
BIT
Bit 0
0
1
0
1
0
1
0
1
Channel Selection Register Description (Subaddress) and Power-Up Condition (PUC) Pin
The THS7327 operates using only a single byte transfer protocol similar to Figure 13 and Figure 15. The internal
subaddress registers and the functionality of each are found in Table 2. When writing to the device, it is required
to send one byte of data to the corresponding internal subaddress. If control of all three channels is desired,
then the master has to cycle through all the subaddresses (channels) one at a time, see the Example – Writing
to the THS7327 section for the proper procedure of writing to the THS7327.
During a read cycle, the THS7327 sends the data in its selected subaddress (or channel) in a single transfer to
the master device requesting the information. See the Example – Reading from the THS7327 section for the
proper procedure on reading from the THS7327.
On power up, the THS7327 registers are dictated by the power-up control (PUC) pin. If the PUC pin is tied to
GND, the THS7327 will power-up in a fully disabled state. If the PUC pin is tied to VDD, upon power-up the
THS7327 will be configured with HV sync on, buffer path disabled, monitor path Enabled, and input bias mode
set to AC-Bias on all input channels. It remains in this state until a valid write sequence is made to the
THS7327. A total of 12 bytes of data completely configures all channels of the THS7327. As such, configuring
the THS7327 is accomplished quickly and easily.
Table 2. THS7327 Channel Selection Register Bit Assignments
REGISTER NAME
Channel 1
Channel 2
Channel 3
Channel H and V Sync and Disable Controls
BIT ADDRESS
(b₇b₆b₅....b₀)
0000 0001
0000 0010
0000 0011
0000 0100
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