THS7327 Datasheet, PDF (17/26 Pages) Texas Instruments – 3-Channel RGBHV Video Buffer with I2C Control, Selectable Filters, Monitor Pass-Thru,2:1 Input MUX, and Selectable Input Bias Modes

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THS7327
SLOS502 – SEPTEMBER 2006
APPLICATION INFORMATION (continued)
• To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from
low to high while the SCL line is high (see Figure 9). This releases the bus and stops the communication link
with the addressed slave. All I²C compatible devices must recognize the stop condition. Upon the receipt of
a stop condition, all devices know that the bus is released, and they wait for a start condition followed by a
matching address.
SDA
SCL
Data Line
Stable;
Data Valid
Change of Data Allowed
Figure 10. I²C Bit Transfer
Data Output
by Transmitter
Data Output
by Receiver
Not Acknowledge
SCL From
Master
1
2
Acknowledge
8
9
S
Start
Condition
Figure 11. I²C Acknowledge
Clock Pulse for
Acknowledgement
SCL
12 3 4 5 6 78 9 123 4 5 67 8 9
SDA
MSB
Acknowledge
Slave Address
Data
Stop
Acknowledge
Figure 12. I²C Address and Data Cycles
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