SM59R16A5 Datasheet, PDF (76/89 Pages) SyncMOS Technologies,Inc – Two serial peripheral interfaces in full duplex mode

SM59R16A5/SM59R09A5/SM59R05A5
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
12 3.0 K bytes ($F400h ~ $FFFFh)
13 3.25 K bytes ($F300h ~ $FFFFh)
14 3.5 K bytes ($F200h ~ $FFFFh)
15 3.75 K bytes ($F100h ~ $FFFFh)
16 4.0 K bytes ($F000h ~ $FFFFh)
ISP service program configurable in N*256 byte (N= 0 ~ 16)
19.3. Program the ISP Service Program
After Lock Bit N is set and ISP service program been programmed, the ISP service program memory will be
protected (locked) automatically. The lock bit N has its own program/erase timing. It is different from the flash
memory program/erase timing so the locked ISP service program can not be erased by flash erase function. If user
needs to erase the locked ISP service program, he can do it by writer only. User can not change ISP service program
when SM59R16A5 was in system.
19.4. Initiate ISP Service Program
To initiate the ISP service program is to load the program counter (PC) with start address of ISP service program and
execute it. There are four ways to do so:
(1) Blank reset. Hardware reset with first flash address blank ($0000=#FFH) will load the PC with start
address of ISP service program. The hardware reset includes Internal (power on reset) and external
pad reset.
(2) Execute jump instruction can load the start address of the ISP service program to PC.
(3) Enters ISP service program by hardware setting. User can force SM59R16A5 enter ISP service
program by setting P2.6, P2.7 “active low” or P4.3 “ active low” during hardware reset period. The
hardware reset includes Internal (power on reset) and external pad reset. In application system
design, user should take care of the setting of P2.6, P2.7 or P4.3 at reset period to prevent
SM59R16A5 from entering ISP service program.
(4) Enter’s ISP service program by hardware setting, the port3.0 will be detected the two clock signals
during hardware reset period. The hardware reset includes Internal (power on reset) and external
pad reset. And detect 2 clock signals after hardware reset.
During hardware reset period, the hardware will detect the status of P2.6/P2.7/P4.3/P3.0. If they meet one of above
conditions, chip will switch to ISP mode automatically. After ISP service program executed, user need to reset the
SM59R16A5, either by hardware reset or by WDT, or jump to the address $0000 to re-start the firmware program.
There are 8 kinds of entry mechanisms for user different applications. This entry method will select on the writer or
ISP.
(1) First Address Blank. i.e. $0000 = 0xFF. And triggered by Internal reset signal.
(2) First Address Blank. i.e. $0000 = 0xFF. And triggered by PAD reset signal.
(3) P2.6 = 0 & P2.7 = 0. And triggered by Internal reset signal.
(4) P2.6 = 0 & P2.7 = 0. And triggered by PAD reset signal.
(5) P4.3 = 0. And triggered by Internal reset signal.
(6) P4.3 = 0. And triggered by PAD reset signal.
(7) P3.0 input 2 clocks. And triggered by Internal reset signal.
(8) P3.0 input 2 clocks. And triggered by PAD reset signal.
19.5. ISP register – TAKEY, IFCON, ISPFAH, ISPFAL, ISPFD and ISPFC
Mnemonic
Description
Direct
TAKEY
Time Access Key
register
F7h
Bit 7
Bit 6 Bit 5
ISP function
Bit 4 Bit 3
TAKEY [7:0]
Bit 2
Bit 1
Bit 0
RESET
00H
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M047
76
Ver.H SM59R16A5 04/2015