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| SM59R16A5 Datasheet, PDF (4/89 Pages) SyncMOS Technologies,Inc – Two serial peripheral interfaces in full duplex mode | |||
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Pin Configuration
SM59R16A5/SM59R09A5/SM59R05A5
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
CC0/T2/ADC0/P1.0 1
CC1/T2EX/ADC1/P1.1 2
RXD1/ADC2/P1.2 3
CC2/TXD1/ADC3/P1.3 4
CC3/SS/ADC4/P1.4 5
MOSI/ADC5/P1.5 6
IIC_SCL/MISO/ADC6/P1.6 7
IIC_SDA/SPI_CLK/ADC7/P1.7 8
P4.7/RESET(default) 9
RXD0/P3.0 10
TXD0/P3.1 11
INT0/P3.2 12
INT1/P3.3 13
T0/P3.4 14
T1/P3.5 15
X32OUT/WR/P3.6 16
X32IN/RD/P3.7 17
X32OUT/P5.4/XTAL2 18
X32IN/P5.5/XTAL1 19
VSS 20
40 VDD
39 P0.0/AD0/KBI0
38 P0.1/AD1/KBI1
37 P0.2/AD2/KBI2
36 P0.3/AD3/KBI3
35 P0.4/AD4/KBI4
34 P0.5/AD5/KBI5
33 P0.6/AD6/KBI6
32 P0.7/AD7/KBI7
31 OCI_SDA/P4.6
30 ALE/P4.5
29 OCI_SCL/P4.4
28 P2.7/A15/KBI7/Op0Out/PWM3
27 P2.6/A14/KBI6/Op0PIn/PWM2
26 P2.5/A13/KBI5/Op0NIn/PWM1
25 P2.4/A12/KBI4/Op1PIn/PWM0
24 P2.3/A11/KBI3/Op1NIn/CC3
23 P2.2/A10/KBI2/Op1Out/CC2
22 P2.1/A9/KBI1/CC1
21 P2.0/A8/KBI0/CC0
Notesï¼
1. The pin Reset/P4.7 factory default is Reset, user must keep this pin at low during power-up. User can configure it to
GPIO (P4.7) by a flash programmer.
2. To avoid accidentally entering ISP-Mode(refer to section 16.4), care must be taken not asserting pulse signal at P3.0
during power-up while P2.6ãP2.7ãP4.3 are set to high.
3. To apply ICP function, OSI_SDA/P4.6 and OCI_SCL/P4.7 must be set to Bi-direction mode if they are configured as
GPIO in system.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M047
4
Ver.H SM59R16A5 04/2015
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