SM59R16A5 Datasheet, PDF (64/89 Pages) SyncMOS Technologies,Inc – Two serial peripheral interfaces in full duplex mode

SM59R16A5/SM59R09A5/SM59R05A5
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
15. SPI function
Serial Peripheral Interface (SPI) is a synchronous protocol that allows a master device to initiate communication with
slave devices.
The interrupt vector is 4Bh.
There are 4 signals used in SPI, they are
SPI_MOSI: data output in the master mode, data input in the slave mode,
SPI_MISO: data input in the master mode, data output in the slave mode,
SPI_SCK: clock output form the master, the above data are synchronous to this signal
SPI_SS: input in the slave mode.
This slave device detects this signal to judge if it is selected by the master.
In the master mode, it can select the desired slave device by any IO with value = 0. Fig. 15-1 is an example showing the
relation of the 4 signals between master and slaves.
Master
MOSI
MISO
CLK
IO
IO
Slave 1
MOSI
MISO
CLK
SS
Slave 2
MOSI
MISO
CLK
SS
Fig. 15-1: SPI signals between master and slave devices
There is only one channel SPI interface. The SPI SFRs are shown as below:
Mnemonic
Description
AUX
SPIC1
SPIC2
SPIS
SPITXD
SPIRXD
Auxiliary register
SPI control register
1
SPI control register
2
SPI status register
SPI transmit data
buffer
SPI receive data
buffer
Direct
91h
F1h
F2h
F5h
F3h
Bit 7
BRGS
SPIEN
Bit 6 Bit 5
SPI function
-
P4SPI
SPIMSS
SPISS
P
Bit 4 Bit 3
P4UR
1
P4IIC
SPICKP SPICKE
Bit 2 Bit 1 Bit 0
P0KBI
P2PW
M
DPS
SPIBR[2:0]
SPIFD
TBC[2:0]
-
RBC[2:0]
- SPIMLS SPIOV SPITXIF SPITDR SPIRXIF SPIRDR SPIRS
SPITXD[7:0]
RESET
00H
08H
00H
40H
00H
F4h
SPIRXD[7:0]
00H
Mnemonic: AUX
7
6
5
BRGS
-
P4SPI
4
P4UR1
3
2
1
P4IIC P0KBI P2PWM
Address: 91h
0 Reset
DPS 00H
P4SPI: P4SPI = 0 – SPI function on P1.
P4SPI = 1 – SPI function on P4.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M047
64
Ver.H SM59R16A5 04/2015