SM59R16A5 Datasheet, PDF (49/89 Pages) SyncMOS Technologies,Inc – Two serial peripheral interfaces in full duplex mode

SM59R16A5/SM59R09A5/SM59R05A5
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
to count from the beginning. The watchdog timer must be refreshed regularly to prevent reset request signal from
becoming active.
When Watchdog timer is overflow, the WDTF flag will set to one and automatically reset MCU. The WDTF flag can be
clear by software or external reset or power on reset.
250KHz RC
oscillator
Clear
Power on reset ^{WDTF = 0}
External reset
Software write “0”
WDTF
TAKEY
(55, AA, 5A)
1
2^WDTM
WDTM[3:0]
Enable WDTC
write attribute
WDTC
WDTEN
WDTCLK
Enable/Disable
WDT
WDT
Counter
Set WDTF = 1
WDT time-out reset
Refresh
WDT Counter
WDTK
(0x55)
Fig. 10-1: Watchdog timer block diagram
Mnemonic
TAKEY
WDTC
WDTK
Description
Time Access Key
register
Watchdog timer
control register
Watchdog timer
refresh key
Direct
F7h
B6h
B7h
Bit 7
WDTF
Bit 6 Bit 5 Bit 4
Watchdog Timer
Bit 3
TAKEY [7:0]
-
WDTE
-
WDTK[7:0]
Bit 2 Bit 1
WDTM [3:0]
Bit 0
RESET
00H
04H
00H
Mnemonic: TAKEY
7
6
5
4
3
2
TAKEY [7:0]
Address: F7h
1
0
Reset
00H
Watchdog timer control register (WDTC) is read-only by default; software must write three specific
values 55h, AAh and 5Ah sequentially to the TAKEY register to enable the WDTC write attribute. That is:
MOV TAKEY, #55h
MOV TAKEY, #AAh
MOV TAKEY, #5Ah
Mnemonic: WDTC
7
6
5
4
WDTF
-
WDTE
-
Address: B6h
3
2
1
0
Reset
WDTM [3:0]
04H
WDTF: Watchdog timer reset flag.
When MCU is reset by watchdog, WDTF flag will be set to one by hardware. This flag
clear by software or external reset or power on reset.
WDTE: Control bit used to enable Watchdog timer.
The WDTE bit can be used only if WDTEN is "0". If the WDTEN bit is "0", then WDT
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M047
49
Ver.H SM59R16A5 04/2015