SM59R16A5 Datasheet, PDF (33/89 Pages) SyncMOS Technologies,Inc – Two serial peripheral interfaces in full duplex mode

SM59R16A5/SM59R09A5/SM59R05A5
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
SLR: Shift direction bit.
SLR = 0 – shift left operation.
SLR = 1 – shift right operation.
SC[4:0]: Shift counter.
When preset with 00000b, normalizing is selected. After normalize sc.0 – sc.4 contains
the number of normalizing shifts performed. When sc.4 – sc.0 ≠ 0, shift operation is
started. The number of shifts performed is determined by the count written to sc.4 to sc.0.
sc.4 – MSB ... sc.0 – LSB
6.2. Operation of the MDU
The operation of the MDU consists of three phases:
6.2.1. First phase: loading the MDx registers, x = 0~5:
The type of calculation the MDU has to perform is selected following the order in which the mdx registers are written to.
Operation
First write
Last write
32bit/16bit
MD0 Dividend Low
MD1 Dividend
MD2 Dividend
MD3 Dividend High
MD4 Divisor Low
MD5 Divisor High
Table 6-1: MDU registers write sequence
16bit/16bit
16bit x 16bit
MD0 Dividend Low
MD0 Multiplicand Low
MD1 Dividend High
MD4 Multiplicator Low
MD1 Multiplicand High
MD4 Divisor Low
MD5 Divisor High
MD5 Multiplicator High
shift/normalizing
MD0 LSB
MD1
MD2
MD3 MSB
ARCON start conversion
A write to md0 is the first transfer to be done in any case. Next writes must be done as shown in table 6.1 to determine
MDU operation. Last write finally starts selected operation.
6.2.2. Second phase: executing calculation.
During executing operation, the MDU works on its own parallel to the CPU. When MDU is finished, the MDUF register will
be set to one by hardware and the flag will clear at next calculation.
Mnemonic: PCON
Address: 87h
7
6
5
4
3
2
1
0
Reset
SMOD MDUF
-
-
-
-
STOP IDLE 40h
MDUF: MDU finish flag.
When MDU is finished, the MDUF will be set by hardware and the bit will clear
by hardware at next calculation.
The following table gives the execution time in every mathematical operation.
Operation
Division 32bit/16bit
Division 16bit/16bit
Multiplication
Shift
Normalize
Table 6-2: MDU execution times
Number of Tclk
17 clock cycles
9 clock cycles
11 clock cycles
Min. 3 clock cycles, Max. 18 clock cycles
Min. 4 clock cycles, Max. 19 clock cycles
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M047
33
Ver.H SM59R16A5 04/2015