SMD1108 Datasheet, PDF (9/29 Pages) Summit Microelectronics, Inc. – 8-Channel Auto-Monitor ADC In System Programmable Analog (ISPA) Device

SMD1108
Preliminary
MEMORY AND REGISTER OPERATION
The SMD1108 incorporates a memory that is configured
as a 128 x 8 array. Concatenated with the memory array
are the sixteen registers that hold the upper and lower
limits for ADC comparison tables. Additional registers
provide space for configuration usage. Another space is
provided for individual channel conversion initiations and
reading the conversion data.
All Read and Write operations to memory are handled via
an industry standard two-wire interface. The bus was
designed for two-way, two-line serial communication
between different integrated circuits. The two lines are a
serial data line (SDA), and a serial clock line (SCL). The
SDA line must be connected to a positive supply by a pull-
up resistor, located somewhere on the bus
Input Data Protocol
The protocol defines any device that sends data onto the
bus as a transmitter and any device that receives data as
a receiver. The device controlling data transmission is
called the Master and the controlled device is called the
Slave. In all cases the SMD1108 will be a Slave device
since it never initiates any data transfers.
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable during clock high
time, because changes on the data line while SCL is high
will be interpreted as a Start or a Stop condition.
START and STOP Conditions
When both the data and clock lines are high the bus is said
to be not busy. A high-to-low transition on the data line,
while the clock is high, is defined as the Start condition.
A low-to-high transition on the data line, while the clock
is high, is defined as the Stop condition.
Acknowledge (ACK)
Acknowledge is a software convention used to indicate
successful data transfers. The transmitting device, either
the Master or the Slave, will release the bus after
transmitting eight bits. During the ninth clock cycle the
receiver will pull the SDA line low to Acknowledge that it
received the eight bits of data.
The SMD1108 will respond with an Acknowledge after
recognition of a Start condition and its Slave address byte.
If both the device and a Write operation are selected, the
SMD1108 will respond with an Acknowledge after the
receipt of each subsequent 8-Bit word. In the Read mode
the SMD1108 transmits eight bits of data, then releases
the SDA line, and monitors the line for an Acknowledge
signal. If an Acknowledge is detected, and no STOP
condition is generated by the master, the SMD1108 will
continue to transmit data. If the Master leaves the SDA
line high (NACK) the SMD1108 will terminate further data
transmissions and await a Stop condition before returning
to the standby power mode.
Device Addressing
Following a start condition the Master must output the
address of the Slave it is accessing. The most significant
four bits of the Slave address are the device type identifier
(DTI). For the SMD1108 the default memory DTI is
1010_BIN. The next three bits in the serial data stream are
the device’s bus address. The bus address is assigned by
biasing the A0, A1 and A2 pins into any one of eight unique
addresses. The last bit of the data stream defines the
operation to be performed: when set to 1 a Read operation
is selected; when set to 0 a Write operation is selected.
MEMORY WRITE OPERATIONS
The SMD1108 allows two types of Write operations: byte
Write and page Write. A byte Write operation writes a
single byte during the nonvolatile write period (tWR). The
page write operation allows up to 16 bytes in the same
page to be written during tWR.
Byte Write
After the Slave address is sent (to identify the Slave
device, and a Read or Write operation), a second byte is
transmitted which contains the 8-Bit address of any one
of the 128 words in the array. Upon receipt of the word
address the SMD1108 responds with an Acknowledge.
After receiving the next byte of data it again responds with
an Acknowledge. The Master then terminates the transfer
by generating a Stop condition, at which time the
SMD1108 begins an internal write cycle. While the
internal write cycle is in progress the SMD1108 inputs are
disabled, and the device will not respond to any requests
from the master.
Page Write
The SMD1108 is capable of a 16-byte page Write opera-
tion. It is initiated in the same manner as the byte Write
operation, but instead of terminating the Write cycle after
the first data word, the Master can transmit up to 15 more
bytes of data. After the receipt of each byte the SMD1108
will respond with an Acknowledge.
SUMMIT MICROELECTRONICS, Inc.
2052 2.0 10/05/01
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