SMD1108 Datasheet, PDF (18/29 Pages) Summit Microelectronics, Inc. – 8-Channel Auto-Monitor ADC In System Programmable Analog (ISPA) Device

SMD1108
Preliminary
Register 8D controls three delays. DRT2, DRT1, and
DRT0 control the hold-off time period for generation of any
IRQ output and define the hold-off for the DLYD_RST#
output. OCD1 and OCD0 define the delay from the first
sensing of an over-current condition, and how long that
condition exists before taking action. FWD1 and FWD0
control the hold-off period from the first sensing of a fault
condition until recording all active conditions.
7
6
FWD1 FWD0
x
x
0
0
0
1
1
0
1
1
5
4
3
2
1
0 Bits
OCD1 OCD0 x
DRT2 DRT1 DRT0
Function
0
x
x Delayed reset timer disabled
1
0
0 200ms Delayed reset timer interval
x
x
1
0
1 400ms Delayed reset timer interval
1
1
0 800ms Delayed reset timer interval
1
1
1 1600ms Delayed reset timer interval
0
0
x
x
x 25µs Over-current trip delay
0
1
x
x
x
x 50µs Over-current trip delay
1
0
x
x
x 100µs Over-current trip delay
1
1
x
x
x 200µs Over-current trip delay
x
x
x
x
x Fault write sense delay off
x
x
x
x
x 50µs Fault write sense delay
x
x
x
x
x 100µs Fault write sense delay
x
x
x
x
x 200µs Fault write sense delay
2052 Table19 1.0
Table 19. Register 8D Reset Pulse Width and Timer Delays
18
2052 2.0 10/05/01
SUMMIT MICROELECTRONICS, Inc.