SMD1108 Datasheet, PDF (13/29 Pages) Summit Microelectronics, Inc. – 8-Channel Auto-Monitor ADC In System Programmable Analog (ISPA) Device

SMD1108
Preliminary
S
T
1001
A
R
T
ACCCCCC
C MMMH H H
WK 2 1 0 2 1 0
CMD Channel
Bits Address
A
C
K
S
T
O
Dummy write sets the channel address
P
S
T
1001
A
R
T
R
A
C
K
N
CCC
HHH
210
DD
98
A
C
K
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
S
T
O
Channel
P
Address
Echoed
Read back of converted data includes
the channel address that is being
converted followed by the data.
optional ACK or NACK/STOP
S
T
1001
A
R
T
R
A
C
K
CCC
HHH
210
DD
98
A
C
K
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
CCC
HHH
210
DD
98
A
C
K
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
S
T
O
P
In a continuous read mode the SMD1108 will clock data out as shown above repeating the channel address for each
conversion that takes place. For the mult-channel conversions the channel numbers increment, e.g., n to n+1.
2052 Fig07 1.0
Figure 7. Continuous Read
M-ADD MSB
LSB
Function
F0
x
x
x
x
x
AR01 D9
D8 Channel #0 low limit
F1
D7
D6
D5
D4
D3
D2
D1
D0 Channel #0 low limit
F2
x
x
x
x
x
AR02 D9
D8 Channel #0 high limit
F3
D7
D6
D5
D4
D3
D2
D1
D0 Channel #0 high limit
F4
x
x
x
x
x
AR11 D9
D8 Channel #1 low limit
F5
D7
D6
D5
D4
D3
D2
D1
D0 Channel #1 low limit
F6
x
x
x
x
x
AR12 D9
D8 Channel #1 high limit
F7
D7
D6
D5
D4
D3
D2
D1
D0 Channel #1 high limit
F8
x
x
x
x
x
AR21 D9
D8 Channel #2 low limit
F9
D7
D6
D5
D4
D3
D2
D1
D0 Channel #2 low limit
FA
x
x
x
x
x
AR22 D9
D8 Channel #2 high limit
FB
D7
D6
D5
D4
D3
D2
D1
D0 Channel #2 high limit
FC
x
x
x
x
x
AR31 D9
D8 Channel #3 low limit
FD
D7
D6
D5
D4
D3
D2
D1
D0 Channel #3 low limit
FE
x
x
x
x
x
AR32 D9
D8 Channel #3 high limit
FF
D7
D6
D5
D4
D3
D2
D1
D0 Channel #3 high limit
Note: ARxx is the Alert Region limit. See Environmental Automonitor Blocks description in the Applications Information section.
2052 Table04
Table 4. ADC Registers Located at the Top of 1001 Address Space
SUMMIT MICROELECTRONICS, Inc.
2052 2.0 10/05/01
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