SMD1108 Datasheet, PDF (22/29 Pages) Summit Microelectronics, Inc. – 8-Channel Auto-Monitor ADC In System Programmable Analog (ISPA) Device

SMD1108
Preliminary
Registers 94 & 95 are similar to FAULT# registers 92 and
93. If any one of the selected sources is true the fault
condition will be recorded in the nonvolatile fault latches
9E and 9F. This in turn will drive the FLT_IRQ# output low.
7
OV3
CH7
0
1
6
OV2
CH6
0
1
5
OV1
CH5
0
1
4
OV0
CH4
0
1
3
2
1
0 Bit
UV3 UV2 UV1 UV0
CH7 CH6 CH5 CH4
Function
0
0
0
0 FAULT# latch unaffected by condition
1
1
1
1 FAULT# latch records out of limit condition
2052 Table26
Table 26. Register 94 FAULT# Latch Mask
7
OC3
CH7
0
1
6
OC2
CH6
0
1
5
OC1
CH5
0
1
4
OC0
CH4
0
1
3
2
1
0 Bit
LIM3 LIM2 LIM1 LIM0
CH3 CH2 CH1 CH0
Function
0
0
0
0 FAULT# latch unaffected by condition
1
1
1
1 FAULT# latch records out of limit condition
Table 27. Register 95 FAULT# Latch Mask
2052 Table27
THE GFS REGISTERS
The balance of the registers can be thought of as the
operation registers. That is, the previous registers define
the part’s function and their contents will most likely be
written once and never altered. The following GPO, fault,
and status registers will be actively read and written
during system operation.
7
6
5
4
3
2
1
0 Bit
GPO3 GPO2 GPO1 GPO0
Function
x
x
x
x
0
0
0
0 Power on state — non-active
1
1
1
1 Corresponding output to ground
2052 Table28 1.0
Table 28. GFS Register 98 GPO Output Control
Register 99 provides a software method for activating a
RESET output or clearing an IRQ (this effectively mimics
the IRQ_RST# input).
7
6
5
4
3
2
1
0 Bit
Reserved
Soft Clear
Reset IRQ
Function
x
1 Clears any IRQ except FLT_IRQ#
0
0
0
0
0
0
1
x
Starts reset cycle, then self clears
Table 29. GFS Register 99 GPO Output Control
2052 Table29 1.0
22
2052 2.0 10/05/01
SUMMIT MICROELECTRONICS, Inc.