SMD1108 Datasheet, PDF (10/29 Pages) Summit Microelectronics, Inc. – 8-Channel Auto-Monitor ADC In System Programmable Analog (ISPA) Device

SMD1108
Preliminary
The SMD1108 automatically increments the address for
subsequent data words. After the receipt of each word the
low order address bits are internally incremented by one.
The high order bits of the address byte remain constant.
Should the Master transmit more than 16 bytes, prior to
generating the Stop condition, the address counter will
rollover, and the previously written data will be overwrit-
ten. As with the byte Write operation all inputs are
disabled during the internal write cycle. Refer to Figure
2 for the address, Acknowledge, and data transfer se-
quence.
Write Cycle
In Progress
Issue Start
Issue Slave
Address and
R/W = 0
Issue Stop
Acknowledge Polling
When the SMD1108 is performing an internal Write
operation it will ignore any new Start conditions. Since the
device will only return an acknowledge after it accepts the
Start, the part can be continuously queried until an
acknowledge is issued, indicating that the internal Write
cycle is complete. See the flow diagram (Figure 3) for the
proper sequence of operations for polling.
ACK
No
Returned
Yes
Next
No
Operation
a Write?
READ OPERATIONS
Read operations are initiated with the R/W bit of the
identification field set to 1. There are two different Read
options: (1) Current Address Byte Read; or (2) Random
Address Byte Read
Yes
Issue
Address
Issue Stop
Current Address Read
The SMD1108 contains an internal address counter which
maintains the address of the last word accessed, incre-
Proceed
With
Write
Await
Next
Command
2052 Fig03
Figure 3. Polling Sequence
S
T
S
A
Typical Write Operation
T
Master
R
T
O
P
SDA
AA
21
A
0
R
/
W
AA A A A A A A
76 5 4 3 2 1 0
DDDDDDDD
76543210
DD
76
DD
10
Slave
A
A
A
A
C
C
C
C
K
K
K
K
S
T
Master
A
R
T
SDA
Slave
Typical Read Operation
AA
21
A
0
R
/
W
A
A
C
C
K
K
DDDDDDDD DDDDDDDD DD
76543210 76543210 76
A
C
K
NS
AT
CO
KP
DD
10
2052 Fig02 2.0
Figure 2. Address, Acknowledge and Data Transfer Sequence
10
2052 2.0 10/05/01
SUMMIT MICROELECTRONICS, Inc.